faults.cc (7640:5286a8a469c5) | faults.cc (7652:f2621206b062) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 67 68template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = 69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 70 71template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = 72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 73 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 67 68template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = 69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 70 71template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = 72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 73 |
74template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = 75 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 76 |
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74Addr 75ArmFault::getVector(ThreadContext *tc) 76{ 77 // ARM ARM B1-3 78 79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 80 81 // panic if SCTLR.VE because I have no idea what to do with vectored --- 126 unchanged lines hidden (view full) --- 208 fsr.fsHigh = bits(status, 4); 209 fsr.domain = domain; 210 fsr.wnr = (write ? 1 : 0); 211 fsr.ext = 0; 212 tc->setMiscReg(T::FsrIndex, fsr); 213 tc->setMiscReg(T::FarIndex, faultAddr); 214} 215 | 77Addr 78ArmFault::getVector(ThreadContext *tc) 79{ 80 // ARM ARM B1-3 81 82 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 83 84 // panic if SCTLR.VE because I have no idea what to do with vectored --- 126 unchanged lines hidden (view full) --- 211 fsr.fsHigh = bits(status, 4); 212 fsr.domain = domain; 213 fsr.wnr = (write ? 1 : 0); 214 fsr.ext = 0; 215 tc->setMiscReg(T::FsrIndex, fsr); 216 tc->setMiscReg(T::FarIndex, faultAddr); 217} 218 |
219void 220FlushPipe::invoke(ThreadContext *tc) { 221 DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 222 223 // Set the PC to the next instruction of the faulting instruction. 224 // Net effect is simply squashing all instructions behind and 225 // start refetching from the next instruction. 226 tc->setPC(tc->readNextPC()); 227 tc->setNextPC(tc->readNextNPC()); 228 tc->setMicroPC(0); 229 tc->setNextMicroPC(1); 230} 231 |
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216template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc); 217template void AbortFault<DataAbort>::invoke(ThreadContext *tc); 218 219// return via SUBS pc, lr, xxx; rfe, movs, ldm 220 | 232template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc); 233template void AbortFault<DataAbort>::invoke(ThreadContext *tc); 234 235// return via SUBS pc, lr, xxx; rfe, movs, ldm 236 |
221 222 | |
223} // namespace ArmISA | 237} // namespace ArmISA |
224 | |