faults.cc (7426:5da64155a605) faults.cc (7585:afbc40280b56)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 122 unchanged lines hidden (view full) ---

131 break;
132 case MODE_ABORT:
133 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
134 break;
135 default:
136 panic("unknown Mode\n");
137 }
138
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 122 unchanged lines hidden (view full) ---

131 break;
132 case MODE_ABORT:
133 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
134 break;
135 default:
136 panic("unknown Mode\n");
137 }
138
139 Addr pc = tc->readPC();
139 Addr pc M5_VAR_USED = tc->readPC();
140 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
140 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
141 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x newVector: %#x\n",
141 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
142 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
143 tc->setPC(newPc);
144 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
145 tc->setMicroPC(0);
146 tc->setNextMicroPC(1);
147}
148
149void

--- 71 unchanged lines hidden --- 		142 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
143 tc->setPC(newPc);
144 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
145 tc->setMicroPC(0);
146 tc->setNextMicroPC(1);
147}
148
149void

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