faults.cc (7362:9ea92e0eb4a9) faults.cc (7400:f6c9b27c4dbe)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
73
74Addr
75ArmFault::getVector(ThreadContext *tc)
76{
77 // ARM ARM B1-3
78
79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
73
74Addr
75ArmFault::getVector(ThreadContext *tc)
76{
77 // ARM ARM B1-3
78
79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
80
80
81 // panic if SCTLR.VE because I have no idea what to do with vectored
82 // interrupts
83 assert(!sctlr.ve);
81 // panic if SCTLR.VE because I have no idea what to do with vectored
82 // interrupts
83 assert(!sctlr.ve);
84
84
85 if (!sctlr.v)
86 return offset();
87 return offset() + HighVecs;
88
89}
90
91#if FULL_SYSTEM
92

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132 case MODE_ABORT:
133 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
134 break;
135 default:
136 panic("unknown Mode\n");
137 }
138
139 Addr pc = tc->readPC();
85 if (!sctlr.v)
86 return offset();
87 return offset() + HighVecs;
88
89}
90
91#if FULL_SYSTEM
92

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132 case MODE_ABORT:
133 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
134 break;
135 default:
136 panic("unknown Mode\n");
137 }
138
139 Addr pc = tc->readPC();
140 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
141 name(), cpsr, pc, tc->readIntReg(INTREG_LR));
142 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
140 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
141 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x newVector: %#x\n",
142 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
143 tc->setPC(newPc);
144 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
145 tc->setMicroPC(0);
146}
147
143 tc->setPC(newPc);
144 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
145 tc->setMicroPC(0);
146}
147
148void
149Reset::invoke(ThreadContext *tc)
150{
151 tc->getCpuPtr()->clearInterrupts();
152 tc->clearArchRegs();
153 ArmFault::invoke(tc);
154}
155
148#else
149
150void
151UndefinedInstruction::invoke(ThreadContext *tc)
152{
153 assert(unknown || mnemonic != NULL);
154 if (unknown) {
155 panic("Attempted to execute unknown instruction "

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157
158void
159UndefinedInstruction::invoke(ThreadContext *tc)
160{
161 assert(unknown || mnemonic != NULL);
162 if (unknown) {
163 panic("Attempted to execute unknown instruction "

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