faults.cc (7302:d9b1ad210629) faults.cc (7362:9ea92e0eb4a9)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "arch/arm/faults.hh"
46#include "cpu/thread_context.hh"
47#include "cpu/base.hh"
48#include "base/trace.hh"
49
50namespace ArmISA
51{
52
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "arch/arm/faults.hh"
46#include "cpu/thread_context.hh"
47#include "cpu/base.hh"
48#include "base/trace.hh"
49
50namespace ArmISA
51{
52
53template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
53template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
54 {"reset", 0x00, MODE_SVC, 0, 0, true, true};
55
54 {"reset", 0x00, MODE_SVC, 0, 0, true, true};
55
56template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
56template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
57 {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
58
57 {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
58
59template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
59template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
60 {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
61
60 {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
61
62template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
62template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
63 {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
64
63 {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
64
65template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
65template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
66 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
67
66 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
67
68template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
68template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
70
69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
70
71template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
71template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
73
74Addr
72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
73
74Addr
75ArmFaultBase::getVector(ThreadContext *tc)
75ArmFault::getVector(ThreadContext *tc)
76{
77 // ARM ARM B1-3
78
79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
80
81 // panic if SCTLR.VE because I have no idea what to do with vectored
82 // interrupts
83 assert(!sctlr.ve);
84
85 if (!sctlr.v)
86 return offset();
87 return offset() + HighVecs;
88
89}
90
91#if FULL_SYSTEM
92
93void
76{
77 // ARM ARM B1-3
78
79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
80
81 // panic if SCTLR.VE because I have no idea what to do with vectored
82 // interrupts
83 assert(!sctlr.ve);
84
85 if (!sctlr.v)
86 return offset();
87 return offset() + HighVecs;
88
89}
90
91#if FULL_SYSTEM
92
93void
94ArmFaultBase::invoke(ThreadContext *tc)
94ArmFault::invoke(ThreadContext *tc)
95{
96 // ARM ARM B1.6.3
97 FaultBase::invoke(tc);
98 countStat()++;
99
100 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
101 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
102 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |

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180
181 // Advance the PC since that won't happen automatically.
182 tc->setPC(tc->readNextPC());
183 tc->setNextPC(tc->readNextNPC());
184}
185
186#endif // FULL_SYSTEM
187
95{
96 // ARM ARM B1.6.3
97 FaultBase::invoke(tc);
98 countStat()++;
99
100 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
101 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
102 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |

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180
181 // Advance the PC since that won't happen automatically.
182 tc->setPC(tc->readNextPC());
183 tc->setNextPC(tc->readNextNPC());
184}
185
186#endif // FULL_SYSTEM
187
188template<class T>
189void
190AbortFault<T>::invoke(ThreadContext *tc)
191{
192 ArmFaultVals<T>::invoke(tc);
193 FSR fsr = 0;
194 fsr.fsLow = bits(status, 3, 0);
195 fsr.fsHigh = bits(status, 4);
196 fsr.domain = domain;
197 fsr.wnr = (write ? 1 : 0);
198 fsr.ext = 0;
199 tc->setMiscReg(T::FsrIndex, fsr);
200 tc->setMiscReg(T::FarIndex, faultAddr);
201}
202
203template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc);
204template void AbortFault<DataAbort>::invoke(ThreadContext *tc);
205
188// return via SUBS pc, lr, xxx; rfe, movs, ldm
189
190
191
192} // namespace ArmISA
193
206// return via SUBS pc, lr, xxx; rfe, movs, ldm
207
208
209
210} // namespace ArmISA
211