faults.cc (7295:afc0f5c08e99) faults.cc (7302:d9b1ad210629)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 97 unchanged lines hidden (view full) ---

106 cpsr.mode = nextMode();
107 cpsr.it1 = cpsr.it2 = 0;
108 cpsr.j = 0;
109
110 cpsr.t = sctlr.te;
111 cpsr.a = cpsr.a | abortDisable();
112 cpsr.f = cpsr.f | fiqDisable();
113 cpsr.i = 1;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 97 unchanged lines hidden (view full) ---

106 cpsr.mode = nextMode();
107 cpsr.it1 = cpsr.it2 = 0;
108 cpsr.j = 0;
109
110 cpsr.t = sctlr.te;
111 cpsr.a = cpsr.a | abortDisable();
112 cpsr.f = cpsr.f | fiqDisable();
113 cpsr.i = 1;
114 cpsr.e = sctlr.ee;
114 tc->setMiscReg(MISCREG_CPSR, cpsr);
115 tc->setIntReg(INTREG_LR, tc->readPC() +
116 (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
117
118 switch (nextMode()) {
119 case MODE_FIQ:
120 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
121 break;

--- 71 unchanged lines hidden --- 		115 tc->setMiscReg(MISCREG_CPSR, cpsr);
116 tc->setIntReg(INTREG_LR, tc->readPC() +
117 (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
118
119 switch (nextMode()) {
120 case MODE_FIQ:
121 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
122 break;

--- 71 unchanged lines hidden ---