faults.cc (7197:21b9790c446d) faults.cc (7295:afc0f5c08e99)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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136 }
137
138 Addr pc = tc->readPC();
139 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
140 name(), cpsr, pc, tc->readIntReg(INTREG_LR));
141 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
142 tc->setPC(newPc);
143 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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136 }
137
138 Addr pc = tc->readPC();
139 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
140 name(), cpsr, pc, tc->readIntReg(INTREG_LR));
141 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
142 tc->setPC(newPc);
143 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
144 tc->setMicroPC(0);
144}
145
146#else
147
148void
149UndefinedInstruction::invoke(ThreadContext *tc)
150{
151 assert(unknown || mnemonic != NULL);

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146
147#else
148
149void
150UndefinedInstruction::invoke(ThreadContext *tc)
151{
152 assert(unknown || mnemonic != NULL);

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