faults.cc (14091:090449e74135) faults.cc (14128:6ed23d07d0d1)
1/*
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
2 * Copyright (c) 2010, 2012-2014, 2016-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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443 } else {
444 toMode = nextMode();
445 toEL = opModeToEL(toMode);
446 }
447
448 if (fromEL > toEL)
449 toEL = fromEL;
450
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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443 } else {
444 toMode = nextMode();
445 toEL = opModeToEL(toMode);
446 }
447
448 if (fromEL > toEL)
449 toEL = fromEL;
450
451 // Check for Set Priviledge Access Never, if PAN is supported
452 AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
453 if (mmfr1.pan) {
454 if (toEL == EL1) {
455 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
456 span = !sctlr.span;
457 }
458
459 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
460 if (toEL == EL2 && hcr.e2h && hcr.tge) {
461 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
462 span = !sctlr.span;
463 }
464 }
465
451 to64 = ELIs64(tc, toEL);
452
453 // The fault specific informations have been updated; it is
454 // now possible to use them inside the fault.
455 faultUpdated = true;
456}
457
458void

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531
532 // The *Disable functions are virtual and different per fault
533 cpsr.a = cpsr.a | abortDisable(tc);
534 cpsr.f = cpsr.f | fiqDisable(tc);
535 cpsr.i = 1;
536 }
537 cpsr.it1 = cpsr.it2 = 0;
538 cpsr.j = 0;
466 to64 = ELIs64(tc, toEL);
467
468 // The fault specific informations have been updated; it is
469 // now possible to use them inside the fault.
470 faultUpdated = true;
471}
472
473void

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546
547 // The *Disable functions are virtual and different per fault
548 cpsr.a = cpsr.a | abortDisable(tc);
549 cpsr.f = cpsr.f | fiqDisable(tc);
550 cpsr.i = 1;
551 }
552 cpsr.it1 = cpsr.it2 = 0;
553 cpsr.j = 0;
554 cpsr.pan = span ? 1 : saved_cpsr.pan;
539 tc->setMiscReg(MISCREG_CPSR, cpsr);
540
541 // Make sure mailbox sets to one always
542 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
543
544 // Clear the exclusive monitor
545 tc->setMiscReg(MISCREG_LOCKFLAG, 0);
546

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630 spsr.nz = tc->readCCReg(CCREG_NZ);
631 spsr.c = tc->readCCReg(CCREG_C);
632 spsr.v = tc->readCCReg(CCREG_V);
633 if (from64) {
634 // Force some bitfields to 0
635 spsr.q = 0;
636 spsr.it1 = 0;
637 spsr.j = 0;
555 tc->setMiscReg(MISCREG_CPSR, cpsr);
556
557 // Make sure mailbox sets to one always
558 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
559
560 // Clear the exclusive monitor
561 tc->setMiscReg(MISCREG_LOCKFLAG, 0);
562

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646 spsr.nz = tc->readCCReg(CCREG_NZ);
647 spsr.c = tc->readCCReg(CCREG_C);
648 spsr.v = tc->readCCReg(CCREG_V);
649 if (from64) {
650 // Force some bitfields to 0
651 spsr.q = 0;
652 spsr.it1 = 0;
653 spsr.j = 0;
638 spsr.res0_23_22 = 0;
639 spsr.ge = 0;
640 spsr.it2 = 0;
641 spsr.t = 0;
642 } else {
643 spsr.ge = tc->readCCReg(CCREG_GE);
644 ITSTATE it = tc->pcState().itstate();
645 spsr.it2 = it.top6;
646 spsr.it1 = it.bottom2;
647 // Force some bitfields to 0
654 spsr.ge = 0;
655 spsr.it2 = 0;
656 spsr.t = 0;
657 } else {
658 spsr.ge = tc->readCCReg(CCREG_GE);
659 ITSTATE it = tc->pcState().itstate();
660 spsr.it2 = it.top6;
661 spsr.it1 = it.bottom2;
662 // Force some bitfields to 0
648 spsr.res0_23_22 = 0;
649 spsr.ss = 0;
650 }
651 tc->setMiscReg(spsr_idx, spsr);
652
653 // Save preferred return address into ELR_ELx
654 Addr curr_pc = tc->pcState().pc();
655 Addr ret_addr = curr_pc;
656 if (from64)

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665 OperatingMode64 mode = 0;
666 mode.spX = 1;
667 mode.el = toEL;
668 mode.width = 0;
669 cpsr.mode = mode;
670 cpsr.daif = 0xf;
671 cpsr.il = 0;
672 cpsr.ss = 0;
663 spsr.ss = 0;
664 }
665 tc->setMiscReg(spsr_idx, spsr);
666
667 // Save preferred return address into ELR_ELx
668 Addr curr_pc = tc->pcState().pc();
669 Addr ret_addr = curr_pc;
670 if (from64)

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679 OperatingMode64 mode = 0;
680 mode.spX = 1;
681 mode.el = toEL;
682 mode.width = 0;
683 cpsr.mode = mode;
684 cpsr.daif = 0xf;
685 cpsr.il = 0;
686 cpsr.ss = 0;
687 cpsr.pan = span ? 1 : spsr.pan;
673 tc->setMiscReg(MISCREG_CPSR, cpsr);
674
675 // If we have a valid instruction then use it to annotate this fault with
676 // extra information. This is used to generate the correct fault syndrome
677 // information
678 ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
679
680 // Set PC to start of exception handler

--- 974 unchanged lines hidden --- 		688 tc->setMiscReg(MISCREG_CPSR, cpsr);
689
690 // If we have a valid instruction then use it to annotate this fault with
691 // extra information. This is used to generate the correct fault syndrome
692 // information
693 ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
694
695 // Set PC to start of exception handler

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