faults.cc (13895:5762b3dc79c6) faults.cc (13896:5a827a65bd1d)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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491 Addr curPc M5_VAR_USED = tc->pcState().pc();
492 ITSTATE it = tc->pcState().itstate();
493 saved_cpsr.it2 = it.top6;
494 saved_cpsr.it1 = it.bottom2;
495
496 // if we have a valid instruction then use it to annotate this fault with
497 // extra information. This is used to generate the correct fault syndrome
498 // information
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 482 unchanged lines hidden (view full) ---

491 Addr curPc M5_VAR_USED = tc->pcState().pc();
492 ITSTATE it = tc->pcState().itstate();
493 saved_cpsr.it2 = it.top6;
494 saved_cpsr.it1 = it.bottom2;
495
496 // if we have a valid instruction then use it to annotate this fault with
497 // extra information. This is used to generate the correct fault syndrome
498 // information
499 if (inst) {
500 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
501 armInst->annotateFault(this);
502 }
499 ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
503
504 // Ensure Secure state if initially in Monitor mode
505 if (have_security && saved_cpsr.mode == MODE_MON) {
506 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
507 if (scr.ns) {
508 scr.ns = 0;
509 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
510 }

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582 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
583 setSyndrome(tc, MISCREG_HSR);
584 break;
585 default:
586 panic("unknown Mode\n");
587 }
588
589 Addr newPc = getVector(tc);
500
501 // Ensure Secure state if initially in Monitor mode
502 if (have_security && saved_cpsr.mode == MODE_MON) {
503 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
504 if (scr.ns) {
505 scr.ns = 0;
506 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
507 }

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579 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
580 setSyndrome(tc, MISCREG_HSR);
581 break;
582 default:
583 panic("unknown Mode\n");
584 }
585
586 Addr newPc = getVector(tc);
590 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
591 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
587 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
588 "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
589 newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
590 std::string());
592 PCState pc(newPc);
593 pc.thumb(cpsr.t);
594 pc.nextThumb(pc.thumb());
595 pc.jazelle(cpsr.j);
596 pc.nextJazelle(pc.jazelle());
597 pc.aarch64(!cpsr.width);
598 pc.nextAArch64(!cpsr.width);
599 pc.illegalExec(false);

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668 mode.el = toEL;
669 mode.width = 0;
670 cpsr.mode = mode;
671 cpsr.daif = 0xf;
672 cpsr.il = 0;
673 cpsr.ss = 0;
674 tc->setMiscReg(MISCREG_CPSR, cpsr);
675
591 PCState pc(newPc);
592 pc.thumb(cpsr.t);
593 pc.nextThumb(pc.thumb());
594 pc.jazelle(cpsr.j);
595 pc.nextJazelle(pc.jazelle());
596 pc.aarch64(!cpsr.width);
597 pc.nextAArch64(!cpsr.width);
598 pc.illegalExec(false);

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667 mode.el = toEL;
668 mode.width = 0;
669 cpsr.mode = mode;
670 cpsr.daif = 0xf;
671 cpsr.il = 0;
672 cpsr.ss = 0;
673 tc->setMiscReg(MISCREG_CPSR, cpsr);
674
675 // If we have a valid instruction then use it to annotate this fault with
676 // extra information. This is used to generate the correct fault syndrome
677 // information
678 ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
679
676 // Set PC to start of exception handler
677 Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
678 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
680 // Set PC to start of exception handler
681 Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
682 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
679 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
683 "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
684 new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
685 std::string());
680 PCState pc(new_pc);
681 pc.aarch64(!cpsr.width);
682 pc.nextAArch64(!cpsr.width);
683 pc.illegalExec(false);
684 tc->pcState(pc);
685
686 PCState pc(new_pc);
687 pc.aarch64(!cpsr.width);
688 pc.nextAArch64(!cpsr.width);
689 pc.illegalExec(false);
690 tc->pcState(pc);
691
686 // If we have a valid instruction then use it to annotate this fault with
687 // extra information. This is used to generate the correct fault syndrome
688 // information
689 if (inst)
690 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
691 // Save exception syndrome
692 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
693 setSyndrome(tc, getSyndromeReg64());
694}
695
692 // Save exception syndrome
693 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
694 setSyndrome(tc, getSyndromeReg64());
695}
696
697ArmStaticInst *
698ArmFault::instrAnnotate(const StaticInstPtr &inst)
699{
700 if (inst) {
701 auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
702 arm_inst->annotateFault(this);
703 return arm_inst;
704 } else {
705 return nullptr;
706 }
707}
708
696Addr
697Reset::getVector(ThreadContext *tc)
698{
699 Addr base;
700
701 // Check for invalid modes
702 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
703 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);

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710Reset::getVector(ThreadContext *tc)
711{
712 Addr base;
713
714 // Check for invalid modes
715 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
716 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);

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