faults.cc (13394:ebe487b6f18a) faults.cc (13396:23277eaae855)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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292 0, 0, 0, 0, false, true, true, EC_UNKNOWN
293);
294
295Addr
296ArmFault::getVector(ThreadContext *tc)
297{
298 Addr base;
299
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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292 0, 0, 0, 0, false, true, true, EC_UNKNOWN
293);
294
295Addr
296ArmFault::getVector(ThreadContext *tc)
297{
298 Addr base;
299
300 // ARM ARM issue C B1.8.1
301 bool haveSecurity = ArmSystem::haveSecurity(tc);
302
303 // Check for invalid modes
304 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
300 // Check for invalid modes
301 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
305 assert(haveSecurity || cpsr.mode != MODE_MON);
302 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
306 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
307
308 switch (cpsr.mode)
309 {
310 case MODE_MON:
311 base = tc->readMiscReg(MISCREG_MVBAR);
312 break;
313 case MODE_HYP:
314 base = tc->readMiscReg(MISCREG_HVBAR);
315 break;
316 default:
317 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
318 if (sctlr.v) {
319 base = HighVecs;
320 } else {
303 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
304
305 switch (cpsr.mode)
306 {
307 case MODE_MON:
308 base = tc->readMiscReg(MISCREG_MVBAR);
309 break;
310 case MODE_HYP:
311 base = tc->readMiscReg(MISCREG_HVBAR);
312 break;
313 default:
314 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
315 if (sctlr.v) {
316 base = HighVecs;
317 } else {
321 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
318 base = ArmSystem::haveSecurity(tc) ?
319 tc->readMiscReg(MISCREG_VBAR) : 0;
322 }
323 break;
324 }
320 }
321 break;
322 }
323
325 return base + offset(tc);
326}
327
328Addr
329ArmFault::getVector64(ThreadContext *tc)
330{
331 Addr vbar;
332 switch (toEL) {

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689 // information
690 if (inst)
691 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
692 // Save exception syndrome
693 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
694 setSyndrome(tc, getSyndromeReg64());
695}
696
324 return base + offset(tc);
325}
326
327Addr
328ArmFault::getVector64(ThreadContext *tc)
329{
330 Addr vbar;
331 switch (toEL) {

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688 // information
689 if (inst)
690 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
691 // Save exception syndrome
692 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
693 setSyndrome(tc, getSyndromeReg64());
694}
695
696Addr
697Reset::getVector(ThreadContext *tc)
698{
699 Addr base;
700
701 // Check for invalid modes
702 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
703 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
704 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
705
706 // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
707 // are mutually exclusive; there is no need to check here for
708 // which register to use since they hold the same value
709 base = tc->readMiscReg(MISCREG_MVBAR);
710
711 return base + offset(tc);
712}
713
697void
698Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
699{
700 if (FullSystem) {
701 tc->getCpuPtr()->clearInterrupts(tc->threadId());
702 tc->clearArchRegs();
703 }
704 if (!ArmSystem::highestELIs64(tc)) {

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710 if (ArmSystem::haveVirtualization(tc) &&
711 !ArmSystem::haveSecurity(tc)) {
712 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
713 cpsr.mode = MODE_HYP;
714 tc->setMiscReg(MISCREG_CPSR, cpsr);
715 }
716 } else {
717 // Advance the PC to the IMPLEMENTATION DEFINED reset value
714void
715Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
716{
717 if (FullSystem) {
718 tc->getCpuPtr()->clearInterrupts(tc->threadId());
719 tc->clearArchRegs();
720 }
721 if (!ArmSystem::highestELIs64(tc)) {

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727 if (ArmSystem::haveVirtualization(tc) &&
728 !ArmSystem::haveSecurity(tc)) {
729 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
730 cpsr.mode = MODE_HYP;
731 tc->setMiscReg(MISCREG_CPSR, cpsr);
732 }
733 } else {
734 // Advance the PC to the IMPLEMENTATION DEFINED reset value
718 PCState pc = ArmSystem::resetAddr64(tc);
735 PCState pc = ArmSystem::resetAddr(tc);
719 pc.aarch64(true);
720 pc.nextAArch64(true);
721 tc->pcState(pc);
722 }
723}
724
725void
726UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)

--- 865 unchanged lines hidden --- 		736 pc.aarch64(true);
737 pc.nextAArch64(true);
738 tc->pcState(pc);
739 }
740}
741
742void
743UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)

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