faults.cc (12789:b28b286fa57d) faults.cc (13394:ebe487b6f18a)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 286 unchanged lines hidden (view full) ---

295Addr
296ArmFault::getVector(ThreadContext *tc)
297{
298 Addr base;
299
300 // ARM ARM issue C B1.8.1
301 bool haveSecurity = ArmSystem::haveSecurity(tc);
302
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 286 unchanged lines hidden (view full) ---

295Addr
296ArmFault::getVector(ThreadContext *tc)
297{
298 Addr base;
299
300 // ARM ARM issue C B1.8.1
301 bool haveSecurity = ArmSystem::haveSecurity(tc);
302
303 // panic if SCTLR.VE because I have no idea what to do with vectored
304 // interrupts
305 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
306 assert(!sctlr.ve);
307 // Check for invalid modes
308 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
309 assert(haveSecurity || cpsr.mode != MODE_MON);
310 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
311
312 switch (cpsr.mode)
313 {
314 case MODE_MON:
315 base = tc->readMiscReg(MISCREG_MVBAR);
316 break;
317 case MODE_HYP:
318 base = tc->readMiscReg(MISCREG_HVBAR);
319 break;
320 default:
303 // Check for invalid modes
304 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
305 assert(haveSecurity || cpsr.mode != MODE_MON);
306 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
307
308 switch (cpsr.mode)
309 {
310 case MODE_MON:
311 base = tc->readMiscReg(MISCREG_MVBAR);
312 break;
313 case MODE_HYP:
314 base = tc->readMiscReg(MISCREG_HVBAR);
315 break;
316 default:
317 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
321 if (sctlr.v) {
322 base = HighVecs;
323 } else {
324 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
325 }
326 break;
327 }
328 return base + offset(tc);

--- 1266 unchanged lines hidden --- 		318 if (sctlr.v) {
319 base = HighVecs;
320 } else {
321 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
322 }
323 break;
324 }
325 return base + offset(tc);

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