faults.cc (12764:5f812c4e0701) faults.cc (12789:b28b286fa57d)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1528
1529SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
1530 : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1531{}
1532
1533bool
1534SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
1535{
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1519 unchanged lines hidden (view full) ---

1528
1529SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
1530 : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1531{}
1532
1533bool
1534SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
1535{
1536 assert(from64);
1537
1538 const bool have_el2 = ArmSystem::haveVirtualization(tc);
1539
1540 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1541 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1542
1543 return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
1544 (hcr.tge || mdcr.tde);
1545}

--- 51 unchanged lines hidden --- 		1536 const bool have_el2 = ArmSystem::haveVirtualization(tc);
1537
1538 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1539 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1540
1541 return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
1542 (hcr.tge || mdcr.tde);
1543}

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