faults.cc (12732:c8b4f25eea9b) faults.cc (12763:37c243ed1112)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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596 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
597 PCState pc(newPc);
598 pc.thumb(cpsr.t);
599 pc.nextThumb(pc.thumb());
600 pc.jazelle(cpsr.j);
601 pc.nextJazelle(pc.jazelle());
602 pc.aarch64(!cpsr.width);
603 pc.nextAArch64(!cpsr.width);
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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596 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
597 PCState pc(newPc);
598 pc.thumb(cpsr.t);
599 pc.nextThumb(pc.thumb());
600 pc.jazelle(cpsr.j);
601 pc.nextJazelle(pc.jazelle());
602 pc.aarch64(!cpsr.width);
603 pc.nextAArch64(!cpsr.width);
604 pc.illegalExec(false);
604 tc->pcState(pc);
605}
606
607void
608ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
609{
610 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
611 MiscRegIndex elr_idx, spsr_idx;

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679
680 // Set PC to start of exception handler
681 Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
682 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
683 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
684 PCState pc(new_pc);
685 pc.aarch64(!cpsr.width);
686 pc.nextAArch64(!cpsr.width);
605 tc->pcState(pc);
606}
607
608void
609ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
610{
611 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
612 MiscRegIndex elr_idx, spsr_idx;

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680
681 // Set PC to start of exception handler
682 Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
683 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
684 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
685 PCState pc(new_pc);
686 pc.aarch64(!cpsr.width);
687 pc.nextAArch64(!cpsr.width);
688 pc.illegalExec(false);
687 tc->pcState(pc);
688
689 // If we have a valid instruction then use it to annotate this fault with
690 // extra information. This is used to generate the correct fault syndrome
691 // information
692 if (inst)
693 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
694 // Save exception syndrome

--- 901 unchanged lines hidden --- 		689 tc->pcState(pc);
690
691 // If we have a valid instruction then use it to annotate this fault with
692 // extra information. This is used to generate the correct fault syndrome
693 // information
694 if (inst)
695 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
696 // Save exception syndrome

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