faults.cc (12571:19063d7d209a) faults.cc (12589:812b72ee214c)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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474 // Invoke exception handler in AArch64 state
475 invoke64(tc, inst);
476 return;
477 }
478
479 // ARMv7 (ARM ARM issue C B1.9)
480
481 bool have_security = ArmSystem::haveSecurity(tc);
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 465 unchanged lines hidden (view full) ---

474 // Invoke exception handler in AArch64 state
475 invoke64(tc, inst);
476 return;
477 }
478
479 // ARMv7 (ARM ARM issue C B1.9)
480
481 bool have_security = ArmSystem::haveSecurity(tc);
482 bool have_virtualization = ArmSystem::haveVirtualization(tc);
483
484 FaultBase::invoke(tc);
485 if (!FullSystem)
486 return;
487 countStat()++;
488
489 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
490 SCR scr = tc->readMiscReg(MISCREG_SCR);

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579 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
580 break;
581 case MODE_UNDEFINED:
582 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
583 if (ec(tc) != EC_UNKNOWN)
584 setSyndrome(tc, MISCREG_HSR);
585 break;
586 case MODE_HYP:
482
483 FaultBase::invoke(tc);
484 if (!FullSystem)
485 return;
486 countStat()++;
487
488 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
489 SCR scr = tc->readMiscReg(MISCREG_SCR);

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578 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
579 break;
580 case MODE_UNDEFINED:
581 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
582 if (ec(tc) != EC_UNKNOWN)
583 setSyndrome(tc, MISCREG_HSR);
584 break;
585 case MODE_HYP:
587 assert(have_virtualization);
586 assert(ArmSystem::haveVirtualization(tc));
588 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
589 setSyndrome(tc, MISCREG_HSR);
590 break;
591 default:
592 panic("unknown Mode\n");
593 }
594
595 Addr newPc = getVector(tc);

--- 995 unchanged lines hidden --- 		587 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
588 setSyndrome(tc, MISCREG_HSR);
589 break;
590 default:
591 panic("unknown Mode\n");
592 }
593
594 Addr newPc = getVector(tc);

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