faults.cc (12569:fe1ff4059715) faults.cc (12570:e32771e88250)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1027 }
1028 }
1029
1030 if (source == ArmFault::AsynchronousExternalAbort) {
1031 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1032 }
1033 // Get effective fault source encoding
1034 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1027 }
1028 }
1029
1030 if (source == ArmFault::AsynchronousExternalAbort) {
1031 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1032 }
1033 // Get effective fault source encoding
1034 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1035 FSR fsr = getFsr(tc);
1036
1037 // source must be determined BEFORE invoking generic routines which will
1038 // try to set hsr etc. and are based upon source!
1039 ArmFaultVals<T>::invoke(tc, inst);
1040
1041 if (!this->to64) { // AArch32
1035
1036 // source must be determined BEFORE invoking generic routines which will
1037 // try to set hsr etc. and are based upon source!
1038 ArmFaultVals<T>::invoke(tc, inst);
1039
1040 if (!this->to64) { // AArch32
1041 FSR fsr = getFsr(tc);
1042 if (cpsr.mode == MODE_HYP) {
1043 tc->setMiscReg(T::HFarIndex, faultAddr);
1044 } else if (stage2) {
1045 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1046 tc->setMiscReg(T::HFarIndex, OVAddr);
1047 } else {
1048 tc->setMiscReg(T::FsrIndex, fsr);
1049 tc->setMiscReg(T::FarIndex, faultAddr);

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1063 OVAddr, faultAddr);
1064 } else {
1065 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1066 }
1067 }
1068}
1069
1070template<class T>
1042 if (cpsr.mode == MODE_HYP) {
1043 tc->setMiscReg(T::HFarIndex, faultAddr);
1044 } else if (stage2) {
1045 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1046 tc->setMiscReg(T::HFarIndex, OVAddr);
1047 } else {
1048 tc->setMiscReg(T::FsrIndex, fsr);
1049 tc->setMiscReg(T::FarIndex, faultAddr);

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1063 OVAddr, faultAddr);
1064 } else {
1065 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1066 }
1067 }
1068}
1069
1070template<class T>
1071FSR
1072AbortFault<T>::getFsr(ThreadContext *tc)
1071void
1072AbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
1073{
1073{
1074 FSR fsr = 0;
1074 srcEncoded = getFaultStatusCode(tc);
1075 if (srcEncoded == ArmFault::FaultSourceInvalid) {
1076 panic("Invalid fault source\n");
1077 }
1078 ArmFault::setSyndrome(tc, syndrome_reg);
1079}
1075
1080
1076 if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) {
1081template<class T>
1082uint8_t
1083AbortFault<T>::getFaultStatusCode(ThreadContext *tc) const
1084{
1085
1086 panic_if(!this->faultUpdated,
1087 "Trying to use un-updated ArmFault internal variables\n");
1088
1089 uint8_t fsc = 0;
1090
1091 if (!this->to64) {
1077 // AArch32
1078 assert(tranMethod != ArmFault::UnknownTran);
1079 if (tranMethod == ArmFault::LpaeTran) {
1092 // AArch32
1093 assert(tranMethod != ArmFault::UnknownTran);
1094 if (tranMethod == ArmFault::LpaeTran) {
1080 srcEncoded = ArmFault::longDescFaultSources[source];
1081 fsr.status = srcEncoded;
1082 fsr.lpae = 1;
1095 fsc = ArmFault::longDescFaultSources[source];
1083 } else {
1096 } else {
1084 srcEncoded = ArmFault::shortDescFaultSources[source];
1085 fsr.fsLow = bits(srcEncoded, 3, 0);
1086 fsr.fsHigh = bits(srcEncoded, 4);
1087 fsr.domain = static_cast<uint8_t>(domain);
1097 fsc = ArmFault::shortDescFaultSources[source];
1088 }
1098 }
1089 fsr.wnr = (write ? 1 : 0);
1090 fsr.ext = 0;
1091 } else {
1092 // AArch64
1099 } else {
1100 // AArch64
1093 srcEncoded = ArmFault::aarch64FaultSources[source];
1101 fsc = ArmFault::aarch64FaultSources[source];
1094 }
1102 }
1095 if (srcEncoded == ArmFault::FaultSourceInvalid) {
1096 panic("Invalid fault source\n");
1103
1104 return fsc;
1105}
1106
1107template<class T>
1108FSR
1109AbortFault<T>::getFsr(ThreadContext *tc) const
1110{
1111 FSR fsr = 0;
1112
1113 auto fsc = getFaultStatusCode(tc);
1114
1115 // AArch32
1116 assert(tranMethod != ArmFault::UnknownTran);
1117 if (tranMethod == ArmFault::LpaeTran) {
1118 fsr.status = fsc;
1119 fsr.lpae = 1;
1120 } else {
1121 fsr.fsLow = bits(fsc, 3, 0);
1122 fsr.fsHigh = bits(fsc, 4);
1123 fsr.domain = static_cast<uint8_t>(domain);
1097 }
1124 }
1125
1126 fsr.wnr = (write ? 1 : 0);
1127 fsr.ext = 0;
1128
1098 return fsr;
1099}
1100
1101template<class T>
1102bool
1103AbortFault<T>::abortDisable(ThreadContext *tc)
1104{
1105 if (ArmSystem::haveSecurity(tc)) {

--- 454 unchanged lines hidden --- 		1129 return fsr;
1130}
1131
1132template<class T>
1133bool
1134AbortFault<T>::abortDisable(ThreadContext *tc)
1135{
1136 if (ArmSystem::haveSecurity(tc)) {

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