faults.cc (12568:c82782e5a84c) faults.cc (12569:fe1ff4059715)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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421 value |= bits(issVal, 19, 0);
422 } else {
423 value |= issVal;
424 }
425 tc->setMiscReg(syndrome_reg, value);
426}
427
428void
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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421 value |= bits(issVal, 19, 0);
422 } else {
423 value |= issVal;
424 }
425 tc->setMiscReg(syndrome_reg, value);
426}
427
428void
429ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
429ArmFault::update(ThreadContext *tc)
430{
431 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
432
430{
431 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
432
433 if (ArmSystem::highestELIs64(tc)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
436 fromEL = opModeToEL(fromMode);
437 if (opModeIs64(fromMode))
438 from64 = true;
433 // Determine source exception level and mode
434 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
435 fromEL = opModeToEL(fromMode);
436 if (opModeIs64(fromMode))
437 from64 = true;
439
438
440 // Determine target exception level
441 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
442 toEL = EL3;
443 } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
444 toEL = EL2;
445 hypRouted = true;
446 } else {
447 toEL = opModeToEL(nextMode());
448 }
439 // Determine target exception level (aarch64) or target execution
440 // mode (aarch32).
441 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
442 toMode = MODE_MON;
443 toEL = EL3;
444 } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
445 toMode = MODE_HYP;
446 toEL = EL2;
447 hypRouted = true;
448 } else {
449 toMode = nextMode();
450 toEL = opModeToEL(toMode);
451 }
449
452
450 if (fromEL > toEL)
451 toEL = fromEL;
453 if (fromEL > toEL)
454 toEL = fromEL;
452
455
453 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) {
454 // Invoke exception handler in AArch64 state
455 to64 = true;
456 invoke64(tc, inst);
457 return;
458 }
456 to64 = ELIs64(tc, toEL);
457
458 // The fault specific informations have been updated; it is
459 // now possible to use them inside the fault.
460 faultUpdated = true;
461}
462
463void
464ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
465{
466
467 // Update fault state informations, like the starting mode (aarch32)
468 // or EL (aarch64) and the ending mode or EL.
469 // From the update function we are also evaluating if the fault must
470 // be handled in AArch64 mode (to64).
471 update(tc);
472
473 if (to64) {
474 // Invoke exception handler in AArch64 state
475 invoke64(tc, inst);
476 return;
459 }
460
461 // ARMv7 (ARM ARM issue C B1.9)
462
463 bool have_security = ArmSystem::haveSecurity(tc);
464 bool have_virtualization = ArmSystem::haveVirtualization(tc);
465
466 FaultBase::invoke(tc);

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484 // if we have a valid instruction then use it to annotate this fault with
485 // extra information. This is used to generate the correct fault syndrome
486 // information
487 if (inst) {
488 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
489 armInst->annotateFault(this);
490 }
491
477 }
478
479 // ARMv7 (ARM ARM issue C B1.9)
480
481 bool have_security = ArmSystem::haveSecurity(tc);
482 bool have_virtualization = ArmSystem::haveVirtualization(tc);
483
484 FaultBase::invoke(tc);

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502 // if we have a valid instruction then use it to annotate this fault with
503 // extra information. This is used to generate the correct fault syndrome
504 // information
505 if (inst) {
506 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
507 armInst->annotateFault(this);
508 }
509
492 if (have_security && routeToMonitor(tc)) {
493 cpsr.mode = MODE_MON;
494 } else if (have_virtualization && routeToHyp(tc)) {
495 cpsr.mode = MODE_HYP;
496 hypRouted = true;
497 } else {
498 cpsr.mode = nextMode();
499 }
500
501 // Ensure Secure state if initially in Monitor mode
502 if (have_security && saved_cpsr.mode == MODE_MON) {
503 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
504 if (scr.ns) {
505 scr.ns = 0;
506 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
507 }
508 }
509
510 // Ensure Secure state if initially in Monitor mode
511 if (have_security && saved_cpsr.mode == MODE_MON) {
512 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
513 if (scr.ns) {
514 scr.ns = 0;
515 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
516 }
517 }
518
519 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
520 cpsr.mode = toMode;
521
510 // some bits are set differently if we have been routed to hyp mode
511 if (cpsr.mode == MODE_HYP) {
512 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
513 cpsr.t = hsctlr.te;
514 cpsr.e = hsctlr.ee;
515 if (!scr.ea) {cpsr.a = 1;}
516 if (!scr.fiq) {cpsr.f = 1;}
517 if (!scr.irq) {cpsr.i = 1;}

--- 1030 unchanged lines hidden --- 		522 // some bits are set differently if we have been routed to hyp mode
523 if (cpsr.mode == MODE_HYP) {
524 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
525 cpsr.t = hsctlr.te;
526 cpsr.e = hsctlr.ee;
527 if (!scr.ea) {cpsr.a = 1;}
528 if (!scr.fiq) {cpsr.f = 1;}
529 if (!scr.irq) {cpsr.i = 1;}

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