faults.cc (12398:5c48d7e08ba0) faults.cc (12402:a90842ce2303)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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386}
387
388void
389ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
390{
391 uint32_t value;
392 uint32_t exc_class = (uint32_t) ec(tc);
393 uint32_t issVal = iss();
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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386}
387
388void
389ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
390{
391 uint32_t value;
392 uint32_t exc_class = (uint32_t) ec(tc);
393 uint32_t issVal = iss();
394
394 assert(!from64 || ArmSystem::highestELIs64(tc));
395
396 value = exc_class << 26;
397
398 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
399 // 0x25) for which the ISS information is not valid (ARMv7).
400 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
401 // valid it is treated as RES1.

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433 if (ArmSystem::highestELIs64(tc)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
436 fromEL = opModeToEL(fromMode);
437 if (opModeIs64(fromMode))
438 from64 = true;
439
440 // Determine target exception level
395 assert(!from64 || ArmSystem::highestELIs64(tc));
396
397 value = exc_class << 26;
398
399 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
400 // 0x25) for which the ISS information is not valid (ARMv7).
401 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
402 // valid it is treated as RES1.

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434 if (ArmSystem::highestELIs64(tc)) { // ARMv8
435 // Determine source exception level and mode
436 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
437 fromEL = opModeToEL(fromMode);
438 if (opModeIs64(fromMode))
439 from64 = true;
440
441 // Determine target exception level
441 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc))
442 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
442 toEL = EL3;
443 toEL = EL3;
443 else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc))
444 } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
444 toEL = EL2;
445 toEL = EL2;
445 else
446 hypRouted = true;
447 } else {
446 toEL = opModeToEL(nextMode());
448 toEL = opModeToEL(nextMode());
449 }
450
447 if (fromEL > toEL)
448 toEL = fromEL;
449
450 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) {
451 // Invoke exception handler in AArch64 state
452 to64 = true;
453 invoke64(tc, inst);
454 return;

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481 // if we have a valid instruction then use it to annotate this fault with
482 // extra information. This is used to generate the correct fault syndrome
483 // information
484 if (inst) {
485 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
486 armInst->annotateFault(this);
487 }
488
451 if (fromEL > toEL)
452 toEL = fromEL;
453
454 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) {
455 // Invoke exception handler in AArch64 state
456 to64 = true;
457 invoke64(tc, inst);
458 return;

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485 // if we have a valid instruction then use it to annotate this fault with
486 // extra information. This is used to generate the correct fault syndrome
487 // information
488 if (inst) {
489 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
490 armInst->annotateFault(this);
491 }
492
489 if (have_security && routeToMonitor(tc))
493 if (have_security && routeToMonitor(tc)) {
490 cpsr.mode = MODE_MON;
494 cpsr.mode = MODE_MON;
491 else if (have_virtualization && routeToHyp(tc))
495 } else if (have_virtualization && routeToHyp(tc)) {
492 cpsr.mode = MODE_HYP;
496 cpsr.mode = MODE_HYP;
493 else
497 hypRouted = true;
498 } else {
494 cpsr.mode = nextMode();
499 cpsr.mode = nextMode();
500 }
495
496 // Ensure Secure state if initially in Monitor mode
497 if (have_security && saved_cpsr.mode == MODE_MON) {
498 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
499 if (scr.ns) {
500 scr.ns = 0;
501 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
502 }

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742 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
743 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
744 return toHyp;
745}
746
747uint32_t
748UndefinedInstruction::iss() const
749{
501
502 // Ensure Secure state if initially in Monitor mode
503 if (have_security && saved_cpsr.mode == MODE_MON) {
504 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
505 if (scr.ns) {
506 scr.ns = 0;
507 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
508 }

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748 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
749 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
750 return toHyp;
751}
752
753uint32_t
754UndefinedInstruction::iss() const
755{
756
757 // If UndefinedInstruction is routed to hypervisor, iss field is 0.
758 if (hypRouted) {
759 return 0;
760 }
761
750 if (overrideEc == EC_INVALID)
751 return issRaw;
752
753 uint32_t new_iss = 0;
754 uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
755
756 dir = bits(machInst, 21, 21);
757 op0 = bits(machInst, 20, 19);

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831 if (from64)
832 return bits(machInst, 20, 5);
833 return 0;
834}
835
836ExceptionClass
837UndefinedInstruction::ec(ThreadContext *tc) const
838{
762 if (overrideEc == EC_INVALID)
763 return issRaw;
764
765 uint32_t new_iss = 0;
766 uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
767
768 dir = bits(machInst, 21, 21);
769 op0 = bits(machInst, 20, 19);

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843 if (from64)
844 return bits(machInst, 20, 5);
845 return 0;
846}
847
848ExceptionClass
849UndefinedInstruction::ec(ThreadContext *tc) const
850{
839 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
851 // If UndefinedInstruction is routed to hypervisor,
852 // HSR.EC field is 0.
853 if (hypRouted)
854 return EC_UNKNOWN;
855 else
856 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
840}
841
842
843HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
844 ArmFaultVals<HypervisorCall>(_machInst, _imm)
845{}
846
847ExceptionClass

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858
859
860HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
861 ArmFaultVals<HypervisorCall>(_machInst, _imm)
862{}
863
864ExceptionClass

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