faults.cc (12259:f787f664d57a) | faults.cc (12299:c54efdd48952) |
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1/* 2 * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 264 unchanged lines hidden (view full) --- 273 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 274 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat() 275}; 276template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { 277 // Some dummy values (SError is AArch64-only) 278 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 279 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() 280}; | 1/* 2 * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 264 unchanged lines hidden (view full) --- 273 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 274 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat() 275}; 276template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { 277 // Some dummy values (SError is AArch64-only) 278 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 279 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() 280}; |
281template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals = { 282 // Some dummy values (SoftwareBreakpoint is AArch64-only) 283 "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 284 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT, FaultStat() 285}; |
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281template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { 282 // Some dummy values 283 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 284 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 285}; 286template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = { 287 // Some dummy values (SPAlignmentFault is AArch64-only) 288 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, --- 1099 unchanged lines hidden (view full) --- 1388 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1389 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1390 1391 toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 1392 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 1393 return toHyp; 1394} 1395 | 286template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { 287 // Some dummy values 288 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 289 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 290}; 291template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = { 292 // Some dummy values (SPAlignmentFault is AArch64-only) 293 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, --- 1099 unchanged lines hidden (view full) --- 1393 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1394 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1395 1396 toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 1397 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 1398 return toHyp; 1399} 1400 |
1401 1402SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 1403 : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 1404{} 1405 1406bool 1407SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 1408{ 1409 assert(from64); 1410 1411 const bool have_el2 = ArmSystem::haveVirtualization(tc); 1412 1413 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 1414 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 1415 1416 return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 1417 (hcr.tge || mdcr.tde); 1418} 1419 |
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1396void 1397ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1398 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 1399 if (!FullSystem) 1400 return; 1401 1402 // Set sev_mailbox to 1, clear the pending interrupt from remote 1403 // SEV execution and let pipeline continue as pcState is still --- 16 unchanged lines hidden (view full) --- 1420template class ArmFaultVals<VirtualInterrupt>; 1421template class ArmFaultVals<FastInterrupt>; 1422template class ArmFaultVals<VirtualFastInterrupt>; 1423template class ArmFaultVals<SupervisorTrap>; 1424template class ArmFaultVals<SecureMonitorTrap>; 1425template class ArmFaultVals<PCAlignmentFault>; 1426template class ArmFaultVals<SPAlignmentFault>; 1427template class ArmFaultVals<SystemError>; | 1420void 1421ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1422 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 1423 if (!FullSystem) 1424 return; 1425 1426 // Set sev_mailbox to 1, clear the pending interrupt from remote 1427 // SEV execution and let pipeline continue as pcState is still --- 16 unchanged lines hidden (view full) --- 1444template class ArmFaultVals<VirtualInterrupt>; 1445template class ArmFaultVals<FastInterrupt>; 1446template class ArmFaultVals<VirtualFastInterrupt>; 1447template class ArmFaultVals<SupervisorTrap>; 1448template class ArmFaultVals<SecureMonitorTrap>; 1449template class ArmFaultVals<PCAlignmentFault>; 1450template class ArmFaultVals<SPAlignmentFault>; 1451template class ArmFaultVals<SystemError>; |
1452template class ArmFaultVals<SoftwareBreakpoint>; |
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1428template class ArmFaultVals<ArmSev>; 1429template class AbortFault<PrefetchAbort>; 1430template class AbortFault<DataAbort>; 1431template class AbortFault<VirtualDataAbort>; 1432 1433 1434IllegalInstSetStateFault::IllegalInstSetStateFault() 1435{} 1436 1437 1438} // namespace ArmISA | 1453template class ArmFaultVals<ArmSev>; 1454template class AbortFault<PrefetchAbort>; 1455template class AbortFault<DataAbort>; 1456template class AbortFault<VirtualDataAbort>; 1457 1458 1459IllegalInstSetStateFault::IllegalInstSetStateFault() 1460{} 1461 1462 1463} // namespace ArmISA |