faults.cc (11581:d6cfd0be73b2) faults.cc (11585:83784c48fb73)
1/*
2 * Copyright (c) 2010, 2012-2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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964 tc->setMiscReg(T::FsrIndex, fsr);
965 tc->setMiscReg(T::FarIndex, faultAddr);
966 }
967 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
968 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
969 } else { // AArch64
970 // Set the FAR register. Nothing else to do if we are in AArch64 state
971 // because the syndrome register has already been set inside invoke64()
1/*
2 * Copyright (c) 2010, 2012-2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 955 unchanged lines hidden (view full) ---

964 tc->setMiscReg(T::FsrIndex, fsr);
965 tc->setMiscReg(T::FarIndex, faultAddr);
966 }
967 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
968 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
969 } else { // AArch64
970 // Set the FAR register. Nothing else to do if we are in AArch64 state
971 // because the syndrome register has already been set inside invoke64()
972 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
972 if (stage2) {
973 // stage 2 fault, set HPFAR_EL2 to the faulting IPA
974 // and FAR_EL2 to the Original VA
975 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr);
976 tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
977
978 DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
979 OVAddr, faultAddr);
980 } else {
981 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
982 }
973 }
974}
975
976template<class T>
977FSR
978AbortFault<T>::getFsr(ThreadContext *tc)
979{
980 FSR fsr = 0;

--- 465 unchanged lines hidden --- 		983 }
984}
985
986template<class T>
987FSR
988AbortFault<T>::getFsr(ThreadContext *tc)
989{
990 FSR fsr = 0;

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