faults.cc (10417:710ee116eb68) faults.cc (11150:a8a64cca231b)
1/*
2 * Copyright (c) 2010, 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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676 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
677 setSyndrome(tc, getSyndromeReg64());
678}
679
680void
681Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
682{
683 if (FullSystem) {
1/*
2 * Copyright (c) 2010, 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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676 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
677 setSyndrome(tc, getSyndromeReg64());
678}
679
680void
681Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
682{
683 if (FullSystem) {
684 tc->getCpuPtr()->clearInterrupts();
684 tc->getCpuPtr()->clearInterrupts(tc->threadId());
685 tc->clearArchRegs();
686 }
687 if (!ArmSystem::highestELIs64(tc)) {
688 ArmFault::invoke(tc, inst);
689 tc->setMiscReg(MISCREG_VMPIDR,
690 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
691
692 // Unless we have SMC code to get us there, boot in HYP!

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933 "override detected.\n");
934 }
935 if (override_LPAE)
936 tranMethod = ArmFault::LpaeTran;
937 }
938 }
939
940 if (source == ArmFault::AsynchronousExternalAbort) {
685 tc->clearArchRegs();
686 }
687 if (!ArmSystem::highestELIs64(tc)) {
688 ArmFault::invoke(tc, inst);
689 tc->setMiscReg(MISCREG_VMPIDR,
690 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
691
692 // Unless we have SMC code to get us there, boot in HYP!

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933 "override detected.\n");
934 }
935 if (override_LPAE)
936 tranMethod = ArmFault::LpaeTran;
937 }
938 }
939
940 if (source == ArmFault::AsynchronousExternalAbort) {
941 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
941 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
942 }
943 // Get effective fault source encoding
944 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
945 FSR fsr = getFsr(tc);
946
947 // source must be determined BEFORE invoking generic routines which will
948 // try to set hsr etc. and are based upon source!
949 ArmFaultVals<T>::invoke(tc, inst);

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1348{}
1349
1350SystemError::SystemError()
1351{}
1352
1353void
1354SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1355{
942 }
943 // Get effective fault source encoding
944 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
945 FSR fsr = getFsr(tc);
946
947 // source must be determined BEFORE invoking generic routines which will
948 // try to set hsr etc. and are based upon source!
949 ArmFaultVals<T>::invoke(tc, inst);

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1348{}
1349
1350SystemError::SystemError()
1351{}
1352
1353void
1354SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1355{
1356 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
1356 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1357 ArmFault::invoke(tc, inst);
1358}
1359
1360bool
1361SystemError::routeToMonitor(ThreadContext *tc) const
1362{
1363 assert(ArmSystem::haveSecurity(tc));
1364 assert(from64);

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1399 DPRINTF(Faults, "Invoking ArmSev Fault\n");
1400 if (!FullSystem)
1401 return;
1402
1403 // Set sev_mailbox to 1, clear the pending interrupt from remote
1404 // SEV execution and let pipeline continue as pcState is still
1405 // valid.
1406 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1357 ArmFault::invoke(tc, inst);
1358}
1359
1360bool
1361SystemError::routeToMonitor(ThreadContext *tc) const
1362{
1363 assert(ArmSystem::haveSecurity(tc));
1364 assert(from64);

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1399 DPRINTF(Faults, "Invoking ArmSev Fault\n");
1400 if (!FullSystem)
1401 return;
1402
1403 // Set sev_mailbox to 1, clear the pending interrupt from remote
1404 // SEV execution and let pipeline continue as pcState is still
1405 // valid.
1406 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1407 tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
1407 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1408}
1409
1410// Instantiate all the templates to make the linker happy
1411template class ArmFaultVals<Reset>;
1412template class ArmFaultVals<UndefinedInstruction>;
1413template class ArmFaultVals<SupervisorCall>;
1414template class ArmFaultVals<SecureMonitorCall>;
1415template class ArmFaultVals<HypervisorCall>;

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1409
1410// Instantiate all the templates to make the linker happy
1411template class ArmFaultVals<Reset>;
1412template class ArmFaultVals<UndefinedInstruction>;
1413template class ArmFaultVals<SupervisorCall>;
1414template class ArmFaultVals<SecureMonitorCall>;
1415template class ArmFaultVals<HypervisorCall>;

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