faults.cc (10367:bf52480abd01) faults.cc (10417:710ee116eb68)
1/*
2 * Copyright (c) 2010, 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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421 value |= bits(issVal, 19, 0);
422 } else {
423 value |= issVal;
424 }
425 tc->setMiscReg(syndrome_reg, value);
426}
427
428void
1/*
2 * Copyright (c) 2010, 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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421 value |= bits(issVal, 19, 0);
422 } else {
423 value |= issVal;
424 }
425 tc->setMiscReg(syndrome_reg, value);
426}
427
428void
429ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
429ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
430{
431 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
432
433 if (ArmSystem::highestELIs64(tc)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
436 fromEL = opModeToEL(fromMode);
437 if (opModeIs64(fromMode))

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582 pc.jazelle(cpsr.j);
583 pc.nextJazelle(pc.jazelle());
584 pc.aarch64(!cpsr.width);
585 pc.nextAArch64(!cpsr.width);
586 tc->pcState(pc);
587}
588
589void
430{
431 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
432
433 if (ArmSystem::highestELIs64(tc)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
436 fromEL = opModeToEL(fromMode);
437 if (opModeIs64(fromMode))

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582 pc.jazelle(cpsr.j);
583 pc.nextJazelle(pc.jazelle());
584 pc.aarch64(!cpsr.width);
585 pc.nextAArch64(!cpsr.width);
586 tc->pcState(pc);
587}
588
589void
590ArmFault::invoke64(ThreadContext *tc, StaticInstPtr inst)
590ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
591{
592 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
593 MiscRegIndex elr_idx, spsr_idx;
594 switch (toEL) {
595 case EL1:
596 elr_idx = MISCREG_ELR_EL1;
597 spsr_idx = MISCREG_SPSR_EL1;
598 break;

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673 if (inst)
674 reinterpret_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
675 // Save exception syndrome
676 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
677 setSyndrome(tc, getSyndromeReg64());
678}
679
680void
591{
592 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
593 MiscRegIndex elr_idx, spsr_idx;
594 switch (toEL) {
595 case EL1:
596 elr_idx = MISCREG_ELR_EL1;
597 spsr_idx = MISCREG_SPSR_EL1;
598 break;

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673 if (inst)
674 reinterpret_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
675 // Save exception syndrome
676 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
677 setSyndrome(tc, getSyndromeReg64());
678}
679
680void
681Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
681Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
682{
683 if (FullSystem) {
684 tc->getCpuPtr()->clearInterrupts();
685 tc->clearArchRegs();
686 }
687 if (!ArmSystem::highestELIs64(tc)) {
688 ArmFault::invoke(tc, inst);
689 tc->setMiscReg(MISCREG_VMPIDR,

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701 PCState pc = ArmSystem::resetAddr64(tc);
702 pc.aarch64(true);
703 pc.nextAArch64(true);
704 tc->pcState(pc);
705 }
706}
707
708void
682{
683 if (FullSystem) {
684 tc->getCpuPtr()->clearInterrupts();
685 tc->clearArchRegs();
686 }
687 if (!ArmSystem::highestELIs64(tc)) {
688 ArmFault::invoke(tc, inst);
689 tc->setMiscReg(MISCREG_VMPIDR,

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701 PCState pc = ArmSystem::resetAddr64(tc);
702 pc.aarch64(true);
703 pc.nextAArch64(true);
704 tc->pcState(pc);
705 }
706}
707
708void
709UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
709UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
710{
711 if (FullSystem) {
712 ArmFault::invoke(tc, inst);
713 return;
714 }
715
716 // If the mnemonic isn't defined this has to be an unknown instruction.
717 assert(unknown || mnemonic != NULL);

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762
763 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
764 Rt << 5 | CRm << 1 | dir;
765
766 return new_iss;
767}
768
769void
710{
711 if (FullSystem) {
712 ArmFault::invoke(tc, inst);
713 return;
714 }
715
716 // If the mnemonic isn't defined this has to be an unknown instruction.
717 assert(unknown || mnemonic != NULL);

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762
763 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
764 Rt << 5 | CRm << 1 | dir;
765
766 return new_iss;
767}
768
769void
770SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
770SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
771{
772 if (FullSystem) {
773 ArmFault::invoke(tc, inst);
774 return;
775 }
776
777 // As of now, there isn't a 32 bit thumb version of this instruction.
778 assert(!machInst.bigThumb);

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879// else if (machInst.thumb)
880// esr.imm16 = bits(machInst.instBits, 7, 0);
881// else
882// esr.imm16 = bits(machInst.instBits, 15, 0);
883// tc->setMiscReg(esr_idx, esr);
884// }
885
886void
771{
772 if (FullSystem) {
773 ArmFault::invoke(tc, inst);
774 return;
775 }
776
777 // As of now, there isn't a 32 bit thumb version of this instruction.
778 assert(!machInst.bigThumb);

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879// else if (machInst.thumb)
880// esr.imm16 = bits(machInst.instBits, 7, 0);
881// else
882// esr.imm16 = bits(machInst.instBits, 15, 0);
883// tc->setMiscReg(esr_idx, esr);
884// }
885
886void
887SecureMonitorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
887SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
888{
889 if (FullSystem) {
890 ArmFault::invoke(tc, inst);
891 return;
892 }
893}
894
895ExceptionClass

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908SecureMonitorTrap::ec(ThreadContext *tc) const
909{
910 return (overrideEc != EC_INVALID) ? overrideEc :
911 (from64 ? EC_SMC_64 : vals.ec);
912}
913
914template<class T>
915void
888{
889 if (FullSystem) {
890 ArmFault::invoke(tc, inst);
891 return;
892 }
893}
894
895ExceptionClass

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908SecureMonitorTrap::ec(ThreadContext *tc) const
909{
910 return (overrideEc != EC_INVALID) ? overrideEc :
911 (from64 ? EC_SMC_64 : vals.ec);
912}
913
914template<class T>
915void
916AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
916AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
917{
918 if (tranMethod == ArmFault::UnknownTran) {
919 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
920 : ArmFault::VmsaTran;
921
922 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
923 // See ARM ARM B3-1416
924 bool override_LPAE = false;

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1232 break;
1233 // Just ignore unknown ID's
1234 default:
1235 break;
1236 }
1237}
1238
1239void
917{
918 if (tranMethod == ArmFault::UnknownTran) {
919 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
920 : ArmFault::VmsaTran;
921
922 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
923 // See ARM ARM B3-1416
924 bool override_LPAE = false;

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1232 break;
1233 // Just ignore unknown ID's
1234 default:
1235 break;
1236 }
1237}
1238
1239void
1240VirtualDataAbort::invoke(ThreadContext *tc, StaticInstPtr inst)
1240VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1241{
1242 AbortFault<VirtualDataAbort>::invoke(tc, inst);
1243 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1244 hcr.va = 0;
1245 tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1246}
1247
1248bool

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1331 }
1332 return true;
1333}
1334
1335VirtualFastInterrupt::VirtualFastInterrupt()
1336{}
1337
1338void
1241{
1242 AbortFault<VirtualDataAbort>::invoke(tc, inst);
1243 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1244 hcr.va = 0;
1245 tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1246}
1247
1248bool

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1331 }
1332 return true;
1333}
1334
1335VirtualFastInterrupt::VirtualFastInterrupt()
1336{}
1337
1338void
1339PCAlignmentFault::invoke(ThreadContext *tc, StaticInstPtr inst)
1339PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1340{
1341 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1342 assert(from64);
1343 // Set the FAR
1344 tc->setMiscReg(getFaultAddrReg64(), faultPC);
1345}
1346
1347SPAlignmentFault::SPAlignmentFault()
1348{}
1349
1350SystemError::SystemError()
1351{}
1352
1353void
1340{
1341 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1342 assert(from64);
1343 // Set the FAR
1344 tc->setMiscReg(getFaultAddrReg64(), faultPC);
1345}
1346
1347SPAlignmentFault::SPAlignmentFault()
1348{}
1349
1350SystemError::SystemError()
1351{}
1352
1353void
1354SystemError::invoke(ThreadContext *tc, StaticInstPtr inst)
1354SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1355{
1356 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
1357 ArmFault::invoke(tc, inst);
1358}
1359
1360bool
1361SystemError::routeToMonitor(ThreadContext *tc) const
1362{

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1377 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1378
1379 toHyp = (!scr.ea && hcr.amo && !inSecureState(scr, cpsr)) ||
1380 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(scr,cpsr));
1381 return toHyp;
1382}
1383
1384void
1355{
1356 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
1357 ArmFault::invoke(tc, inst);
1358}
1359
1360bool
1361SystemError::routeToMonitor(ThreadContext *tc) const
1362{

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1377 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1378
1379 toHyp = (!scr.ea && hcr.amo && !inSecureState(scr, cpsr)) ||
1380 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(scr,cpsr));
1381 return toHyp;
1382}
1383
1384void
1385FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
1385FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1386 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
1387
1388 // Set the PC to the next instruction of the faulting instruction.
1389 // Net effect is simply squashing all instructions behind and
1390 // start refetching from the next instruction.
1391 PCState pc = tc->pcState();
1392 assert(inst);
1393 inst->advancePC(pc);
1394 tc->pcState(pc);
1395}
1396
1397void
1386 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
1387
1388 // Set the PC to the next instruction of the faulting instruction.
1389 // Net effect is simply squashing all instructions behind and
1390 // start refetching from the next instruction.
1391 PCState pc = tc->pcState();
1392 assert(inst);
1393 inst->advancePC(pc);
1394 tc->pcState(pc);
1395}
1396
1397void
1398ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
1398ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1399 DPRINTF(Faults, "Invoking ArmSev Fault\n");
1400 if (!FullSystem)
1401 return;
1402
1403 // Set sev_mailbox to 1, clear the pending interrupt from remote
1404 // SEV execution and let pipeline continue as pcState is still
1405 // valid.
1406 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);

--- 34 unchanged lines hidden --- 		1399 DPRINTF(Faults, "Invoking ArmSev Fault\n");
1400 if (!FullSystem)
1401 return;
1402
1403 // Set sev_mailbox to 1, clear the pending interrupt from remote
1404 // SEV execution and let pipeline continue as pcState is still
1405 // valid.
1406 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);

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