14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#include "arch/arm/faults.hh" 46#include "cpu/thread_context.hh" 47#include "cpu/base.hh" 48#include "base/trace.hh" 49 50namespace ArmISA 51{ 52 53template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals = 54 {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 55 56template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals = 57 {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 58 59template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals = 60 {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 61 62template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals = 63 {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 64 65template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals = 66 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 67 68template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals = 69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 70 71template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals = 72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 73 74Addr 75ArmFaultBase::getVector(ThreadContext *tc) 76{ 77 // ARM ARM B1-3 78 79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 80 81 // panic if SCTLR.VE because I have no idea what to do with vectored 82 // interrupts 83 assert(!sctlr.ve); 84 85 if (!sctlr.v) 86 return offset(); 87 return offset() + HighVecs; 88 89} 90 91#if FULL_SYSTEM 92 93void 94ArmFaultBase::invoke(ThreadContext *tc) 95{ 96 // ARM ARM B1.6.3 97 FaultBase::invoke(tc); 98 countStat()++; 99 100 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 101 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 102 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 103 tc->readIntReg(INTREG_CONDCODES); 104 105 106 cpsr.mode = nextMode(); 107 cpsr.it1 = cpsr.it2 = 0; 108 cpsr.j = 0; 109
|