1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 60 unchanged lines hidden (view full) --- 69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 70 71template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = 72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 73 74template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = 75 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 76 |
77template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals = 78 {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 79 |
80Addr 81ArmFault::getVector(ThreadContext *tc) 82{ 83 // ARM ARM B1-3 84 85 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 86 87 // panic if SCTLR.VE because I have no idea what to do with vectored --- 135 unchanged lines hidden (view full) --- 223 // start refetching from the next instruction. 224 PCState pc = tc->pcState(); 225 assert(inst); 226 pc.forcedItState(inst->machInst.newItstate); 227 inst->advancePC(pc); 228 tc->pcState(pc); 229} 230 |
231void 232ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) { 233 DPRINTF(Faults, "Invoking ReExec Fault\n"); 234 235 // Set the PC to then the faulting instruction. 236 // Net effect is simply squashing all instructions including this 237 // instruction and refetching/rexecuting current instruction 238 PCState pc = tc->pcState(); 239 tc->pcState(pc); 240} 241 |
242template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc, 243 StaticInstPtr inst); 244template void AbortFault<DataAbort>::invoke(ThreadContext *tc, 245 StaticInstPtr inst); 246 247// return via SUBS pc, lr, xxx; rfe, movs, ldm 248 249} // namespace ArmISA |