29,30c29,30
< * Authors: Gabe Black
< * Stephen Hines
---
> * Authors: Ali Saidi
> * Gabe Black
37,40d36
< #if !FULL_SYSTEM
< #include "sim/process.hh"
< #include "mem/page_table.hh"
< #endif
45,47c41,42
< FaultName MachineCheckFault::_name = "Machine Check";
< FaultVect MachineCheckFault::_vect = 0x0401;
< FaultStat MachineCheckFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
> {"reset", 0x00, MODE_SVC, 0, 0, true, true};
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< FaultName AlignmentFault::_name = "Alignment";
< FaultVect AlignmentFault::_vect = 0x0301;
< FaultStat AlignmentFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
> {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
53,59c47,48
< FaultName ResetFault::_name = "Reset Fault";
< #if FULL_SYSTEM
< FaultVect ResetFault::_vect = 0xBFC00000;
< #else
< FaultVect ResetFault::_vect = 0x001;
< #endif
< FaultStat ResetFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
> {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
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< FaultName AddressErrorFault::_name = "Address Error";
< FaultVect AddressErrorFault::_vect = 0x0180;
< FaultStat AddressErrorFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
> {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65,67c53,54
< FaultName StoreAddressErrorFault::_name = "Store Address Error";
< FaultVect StoreAddressErrorFault::_vect = 0x0180;
< FaultStat StoreAddressErrorFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
> {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68a56,57
> template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
> {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
70,72c59,60
< FaultName SystemCallFault::_name = "Syscall";
< FaultVect SystemCallFault::_vect = 0x0180;
< FaultStat SystemCallFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
> {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74,169c62,63
< FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
< FaultVect CoprocessorUnusableFault::_vect = 0x180;
< FaultStat CoprocessorUnusableFault::_count;
<
< FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
< FaultVect ReservedInstructionFault::_vect = 0x0180;
< FaultStat ReservedInstructionFault::_count;
<
< FaultName ThreadFault::_name = "Thread Fault";
< FaultVect ThreadFault::_vect = 0x00F1;
< FaultStat ThreadFault::_count;
<
<
< FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
< FaultVect ArithmeticFault::_vect = 0x180;
< FaultStat ArithmeticFault::_count;
<
< FaultName UnimplementedOpcodeFault::_name = "opdec";
< FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
< FaultStat UnimplementedOpcodeFault::_count;
<
< FaultName InterruptFault::_name = "interrupt";
< FaultVect InterruptFault::_vect = 0x0180;
< FaultStat InterruptFault::_count;
<
< FaultName TrapFault::_name = "Trap";
< FaultVect TrapFault::_vect = 0x0180;
< FaultStat TrapFault::_count;
<
< FaultName BreakpointFault::_name = "Breakpoint";
< FaultVect BreakpointFault::_vect = 0x0180;
< FaultStat BreakpointFault::_count;
<
<
< FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
< FaultVect ItbInvalidFault::_vect = 0x0180;
< FaultStat ItbInvalidFault::_count;
<
< FaultName ItbPageFault::_name = "itbmiss";
< FaultVect ItbPageFault::_vect = 0x0181;
< FaultStat ItbPageFault::_count;
<
< FaultName ItbMissFault::_name = "itbmiss";
< FaultVect ItbMissFault::_vect = 0x0181;
< FaultStat ItbMissFault::_count;
<
< FaultName ItbAcvFault::_name = "iaccvio";
< FaultVect ItbAcvFault::_vect = 0x0081;
< FaultStat ItbAcvFault::_count;
<
< FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
< FaultVect ItbRefillFault::_vect = 0x0180;
< FaultStat ItbRefillFault::_count;
<
< FaultName NDtbMissFault::_name = "dtb_miss_single";
< FaultVect NDtbMissFault::_vect = 0x0201;
< FaultStat NDtbMissFault::_count;
<
< FaultName PDtbMissFault::_name = "dtb_miss_double";
< FaultVect PDtbMissFault::_vect = 0x0281;
< FaultStat PDtbMissFault::_count;
<
< FaultName DtbPageFault::_name = "dfault";
< FaultVect DtbPageFault::_vect = 0x0381;
< FaultStat DtbPageFault::_count;
<
< FaultName DtbAcvFault::_name = "dfault";
< FaultVect DtbAcvFault::_vect = 0x0381;
< FaultStat DtbAcvFault::_count;
<
< FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
< FaultVect DtbInvalidFault::_vect = 0x0180;
< FaultStat DtbInvalidFault::_count;
<
< FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
< FaultVect DtbRefillFault::_vect = 0x0180;
< FaultStat DtbRefillFault::_count;
<
< FaultName TLBModifiedFault::_name = "TLB Modified Exception";
< FaultVect TLBModifiedFault::_vect = 0x0180;
< FaultStat TLBModifiedFault::_count;
<
< FaultName FloatEnableFault::_name = "float_enable_fault";
< FaultVect FloatEnableFault::_vect = 0x0581;
< FaultStat FloatEnableFault::_count;
<
< FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
< FaultVect IntegerOverflowFault::_vect = 0x0501;
< FaultStat IntegerOverflowFault::_count;
<
< FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
< FaultVect DspStateDisabledFault::_vect = 0x001a;
< FaultStat DspStateDisabledFault::_count;
<
< #if FULL_SYSTEM
< void ArmFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
---
> Addr
> ArmFaultBase::getVector(ThreadContext *tc)
171,174c65
< tc->setPC(HandlerBase);
< tc->setNextPC(HandlerBase+sizeof(MachInst));
< tc->setNextNPC(HandlerBase+2*sizeof(MachInst));
< }
---
> // ARM ARM B1-3
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< void ArmFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
< {
< // modify SRS Ctl - Save CSS, put ESS into CSS
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1)
< {
< // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
< MiscReg srs = tc->readMiscReg(ArmISA::SRSCtl);
< uint8_t CSS,ESS;
< CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO);
< ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO);
< // Move CSS to PSS
< replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS);
< // Move ESS to CSS
< replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
< tc->setMiscRegNoEffect(ArmISA::SRSCtl,srs);
< //tc->setShadowSet(ESS);
< }
---
> SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
>
> // panic if SCTLR.VE because I have no idea what to do with vectored
> // interrupts
> assert(!sctlr.ve);
>
> if (!sctlr.v)
> return offset();
> return offset() + HighVecs;
195,221d76
< // set EXL bit (don't care if it is already set!)
< replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1);
< tc->setMiscRegNoEffect(ArmISA::Status,stat);
<
< // write EPC
< // warn("Set EPC to %x\n",tc->readPC());
< // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
< // Check to see if the exception occurred in the branch delay slot
< DPRINTF(Arm,"PC: %x, NextPC: %x, NNPC: %x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC());
< int C_BD=0;
< if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){
< tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC()-sizeof(MachInst));
< // In the branch delay slot? set CAUSE_31
< C_BD = 1;
< } else {
< tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC());
< // In the branch delay slot? reset CAUSE_31
< C_BD = 0;
< }
<
< // Set Cause_EXCCODE field
< MiscReg cause = tc->readMiscReg(ArmISA::Cause);
< replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode);
< replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD);
< replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0);
< tc->setMiscRegNoEffect(ArmISA::Cause,cause);
<
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< void ArithmeticFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0xC);
---
> #if FULL_SYSTEM
229,242c81,82
< // Set new PC
< Addr HandlerBase;
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< // Here, the handler is dependent on BEV, which is not modified by setExceptionState()
< if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase);
< }else{
< HandlerBase = 0xBFC00200;
< }
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< }
<
< void StoreAddressErrorFault::invoke(ThreadContext *tc)
---
> void
> ArmFaultBase::invoke(ThreadContext *tc)
244,246c84,86
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x5);
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
---
> // ARM ARM B1.6.3
> FaultBase::invoke(tc);
> countStat()++;
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< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
---
> SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
> CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
> CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
> tc->readIntReg(INTREG_CONDCODES);
>
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< }
---
> cpsr.mode = nextMode();
> cpsr.it1 = cpsr.it2 = 0;
> cpsr.j = 0;
>
> if (sctlr.te)
> cpsr.t = 1;
> cpsr.a = cpsr.a | abortDisable();
> cpsr.f = cpsr.f | fiqDisable();
> cpsr.i = 1;
> tc->setMiscReg(MISCREG_CPSR, cpsr);
> tc->setIntReg(INTREG_LR, tc->readPC() +
> (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
257,268c107,130
< void TrapFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< // warn("%s encountered.\n", name());
< setExceptionState(tc,0xD);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
---
> switch (nextMode()) {
> case MODE_FIQ:
> tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
> break;
> case MODE_IRQ:
> tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
> break;
> case MODE_SVC:
> tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
> break;
> case MODE_UNDEFINED:
> tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
> break;
> case MODE_ABORT:
> tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
> break;
> default:
> panic("unknown Mode\n");
> }
>
> DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr,
> tc->readPC(), tc->readIntReg(INTREG_LR));
> tc->setPC(getVector(tc));
> tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 );
270,449d131
<
< void BreakpointFault::invoke(ThreadContext *tc)
< {
< setExceptionState(tc,0x9);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
<
< }
<
< void DtbInvalidFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< // warn("%s encountered.\n", name());
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
< setExceptionState(tc,0x3);
<
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
< }
<
< void AddressErrorFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x4);
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< }
<
< void ItbInvalidFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x2);
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< DPRINTF(Arm,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
< }
<
< void ItbRefillFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered (%x).\n", name(),BadVAddr);
< Addr HandlerBase;
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< // Since handler depends on EXL bit, must check EXL bit before setting it!!
< if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< }else{
< HandlerBase = tc->readMiscReg(ArmISA::EBase); // Offset 0x000
< }
<
< setExceptionState(tc,0x2);
< setHandlerPC(HandlerBase,tc);
< }
<
< void DtbRefillFault::invoke(ThreadContext *tc)
< {
< // Set new PC
< DPRINTF(Arm,"%s encountered.\n", name());
< Addr HandlerBase;
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< // Since handler depends on EXL bit, must check EXL bit before setting it!!
< if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< }else{
< HandlerBase = tc->readMiscReg(ArmISA::EBase); // Offset 0x000
< }
<
<
< setExceptionState(tc,0x3);
<
< setHandlerPC(HandlerBase,tc);
< }
<
< void TLBModifiedFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setExceptionState(tc,0x1);
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
<
< }
<
< void SystemCallFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x8);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
<
< }
<
< void InterruptFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x0A);
< Addr HandlerBase;
<
<
< uint8_t IV = bits(tc->readMiscRegNoEffect(ArmISA::Cause),Cause_IV);
< if (IV)// Offset 200 for release 2
< HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(ArmISA::EBase);
< else//Ofset at 180 for release 1
< HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase);
<
< setHandlerPC(HandlerBase,tc);
< #endif
< }
<
452,461c134
< void ResetFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< /* All reset activity must be invoked from here */
< tc->setPC(vect());
< tc->setNextPC(vect()+sizeof(MachInst));
< tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
< DPRINTF(Arm,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
< #endif
---
> // return via SUBS pc, lr, xxx; rfe, movs, ldm
463,465d135
< // Set Coprocessor 1 (Floating Point) To Usable
< //tc->setMiscReg(ArmISA::Status, ArmISA::Status | 0x20000000);
< }
467,478d136
< void ReservedInstructionFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x0A);
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< #else
< panic("%s encountered.\n", name());
< #endif
< }
480,511d137
< void ThreadFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< panic("%s encountered.\n", name());
< }
<
< void DspStateDisabledFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< panic("%s encountered.\n", name());
< }
<
< void CoprocessorUnusableFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0xb);
< /* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */
< MiscReg cause = tc->readMiscReg(ArmISA::Cause);
< replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID);
< tc->setMiscRegNoEffect(ArmISA::Cause,cause);
<
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
<
< // warn("Status: %x, Cause: %x\n",tc->readMiscReg(ArmISA::Status),tc->readMiscReg(ArmISA::Cause));
< #else
< warn("%s (CP%d) encountered.\n", name(), coProcID);
< #endif
< }
<
< * Authors: Gabe Black
< * Stephen Hines
---
> * Authors: Ali Saidi
> * Gabe Black
37,40d36
< #if !FULL_SYSTEM
< #include "sim/process.hh"
< #include "mem/page_table.hh"
< #endif
45,47c41,42
< FaultName MachineCheckFault::_name = "Machine Check";
< FaultVect MachineCheckFault::_vect = 0x0401;
< FaultStat MachineCheckFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
> {"reset", 0x00, MODE_SVC, 0, 0, true, true};
49,51c44,45
< FaultName AlignmentFault::_name = "Alignment";
< FaultVect AlignmentFault::_vect = 0x0301;
< FaultStat AlignmentFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
> {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
53,59c47,48
< FaultName ResetFault::_name = "Reset Fault";
< #if FULL_SYSTEM
< FaultVect ResetFault::_vect = 0xBFC00000;
< #else
< FaultVect ResetFault::_vect = 0x001;
< #endif
< FaultStat ResetFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
> {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
61,63c50,51
< FaultName AddressErrorFault::_name = "Address Error";
< FaultVect AddressErrorFault::_vect = 0x0180;
< FaultStat AddressErrorFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
> {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65,67c53,54
< FaultName StoreAddressErrorFault::_name = "Store Address Error";
< FaultVect StoreAddressErrorFault::_vect = 0x0180;
< FaultStat StoreAddressErrorFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
> {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68a56,57
> template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
> {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
70,72c59,60
< FaultName SystemCallFault::_name = "Syscall";
< FaultVect SystemCallFault::_vect = 0x0180;
< FaultStat SystemCallFault::_count;
---
> template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
> {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74,169c62,63
< FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
< FaultVect CoprocessorUnusableFault::_vect = 0x180;
< FaultStat CoprocessorUnusableFault::_count;
<
< FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
< FaultVect ReservedInstructionFault::_vect = 0x0180;
< FaultStat ReservedInstructionFault::_count;
<
< FaultName ThreadFault::_name = "Thread Fault";
< FaultVect ThreadFault::_vect = 0x00F1;
< FaultStat ThreadFault::_count;
<
<
< FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
< FaultVect ArithmeticFault::_vect = 0x180;
< FaultStat ArithmeticFault::_count;
<
< FaultName UnimplementedOpcodeFault::_name = "opdec";
< FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
< FaultStat UnimplementedOpcodeFault::_count;
<
< FaultName InterruptFault::_name = "interrupt";
< FaultVect InterruptFault::_vect = 0x0180;
< FaultStat InterruptFault::_count;
<
< FaultName TrapFault::_name = "Trap";
< FaultVect TrapFault::_vect = 0x0180;
< FaultStat TrapFault::_count;
<
< FaultName BreakpointFault::_name = "Breakpoint";
< FaultVect BreakpointFault::_vect = 0x0180;
< FaultStat BreakpointFault::_count;
<
<
< FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
< FaultVect ItbInvalidFault::_vect = 0x0180;
< FaultStat ItbInvalidFault::_count;
<
< FaultName ItbPageFault::_name = "itbmiss";
< FaultVect ItbPageFault::_vect = 0x0181;
< FaultStat ItbPageFault::_count;
<
< FaultName ItbMissFault::_name = "itbmiss";
< FaultVect ItbMissFault::_vect = 0x0181;
< FaultStat ItbMissFault::_count;
<
< FaultName ItbAcvFault::_name = "iaccvio";
< FaultVect ItbAcvFault::_vect = 0x0081;
< FaultStat ItbAcvFault::_count;
<
< FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
< FaultVect ItbRefillFault::_vect = 0x0180;
< FaultStat ItbRefillFault::_count;
<
< FaultName NDtbMissFault::_name = "dtb_miss_single";
< FaultVect NDtbMissFault::_vect = 0x0201;
< FaultStat NDtbMissFault::_count;
<
< FaultName PDtbMissFault::_name = "dtb_miss_double";
< FaultVect PDtbMissFault::_vect = 0x0281;
< FaultStat PDtbMissFault::_count;
<
< FaultName DtbPageFault::_name = "dfault";
< FaultVect DtbPageFault::_vect = 0x0381;
< FaultStat DtbPageFault::_count;
<
< FaultName DtbAcvFault::_name = "dfault";
< FaultVect DtbAcvFault::_vect = 0x0381;
< FaultStat DtbAcvFault::_count;
<
< FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
< FaultVect DtbInvalidFault::_vect = 0x0180;
< FaultStat DtbInvalidFault::_count;
<
< FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
< FaultVect DtbRefillFault::_vect = 0x0180;
< FaultStat DtbRefillFault::_count;
<
< FaultName TLBModifiedFault::_name = "TLB Modified Exception";
< FaultVect TLBModifiedFault::_vect = 0x0180;
< FaultStat TLBModifiedFault::_count;
<
< FaultName FloatEnableFault::_name = "float_enable_fault";
< FaultVect FloatEnableFault::_vect = 0x0581;
< FaultStat FloatEnableFault::_count;
<
< FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
< FaultVect IntegerOverflowFault::_vect = 0x0501;
< FaultStat IntegerOverflowFault::_count;
<
< FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
< FaultVect DspStateDisabledFault::_vect = 0x001a;
< FaultStat DspStateDisabledFault::_count;
<
< #if FULL_SYSTEM
< void ArmFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
---
> Addr
> ArmFaultBase::getVector(ThreadContext *tc)
171,174c65
< tc->setPC(HandlerBase);
< tc->setNextPC(HandlerBase+sizeof(MachInst));
< tc->setNextNPC(HandlerBase+2*sizeof(MachInst));
< }
---
> // ARM ARM B1-3
176,193c67,75
< void ArmFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
< {
< // modify SRS Ctl - Save CSS, put ESS into CSS
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1)
< {
< // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
< MiscReg srs = tc->readMiscReg(ArmISA::SRSCtl);
< uint8_t CSS,ESS;
< CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO);
< ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO);
< // Move CSS to PSS
< replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS);
< // Move ESS to CSS
< replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
< tc->setMiscRegNoEffect(ArmISA::SRSCtl,srs);
< //tc->setShadowSet(ESS);
< }
---
> SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
>
> // panic if SCTLR.VE because I have no idea what to do with vectored
> // interrupts
> assert(!sctlr.ve);
>
> if (!sctlr.v)
> return offset();
> return offset() + HighVecs;
195,221d76
< // set EXL bit (don't care if it is already set!)
< replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1);
< tc->setMiscRegNoEffect(ArmISA::Status,stat);
<
< // write EPC
< // warn("Set EPC to %x\n",tc->readPC());
< // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
< // Check to see if the exception occurred in the branch delay slot
< DPRINTF(Arm,"PC: %x, NextPC: %x, NNPC: %x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC());
< int C_BD=0;
< if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){
< tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC()-sizeof(MachInst));
< // In the branch delay slot? set CAUSE_31
< C_BD = 1;
< } else {
< tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC());
< // In the branch delay slot? reset CAUSE_31
< C_BD = 0;
< }
<
< // Set Cause_EXCCODE field
< MiscReg cause = tc->readMiscReg(ArmISA::Cause);
< replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode);
< replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD);
< replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0);
< tc->setMiscRegNoEffect(ArmISA::Cause,cause);
<
224,227c79
< void ArithmeticFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0xC);
---
> #if FULL_SYSTEM
229,242c81,82
< // Set new PC
< Addr HandlerBase;
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< // Here, the handler is dependent on BEV, which is not modified by setExceptionState()
< if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase);
< }else{
< HandlerBase = 0xBFC00200;
< }
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< }
<
< void StoreAddressErrorFault::invoke(ThreadContext *tc)
---
> void
> ArmFaultBase::invoke(ThreadContext *tc)
244,246c84,86
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x5);
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
---
> // ARM ARM B1.6.3
> FaultBase::invoke(tc);
> countStat()++;
248,253c88,92
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
---
> SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
> CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
> CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
> tc->readIntReg(INTREG_CONDCODES);
>
255c94,105
< }
---
> cpsr.mode = nextMode();
> cpsr.it1 = cpsr.it2 = 0;
> cpsr.j = 0;
>
> if (sctlr.te)
> cpsr.t = 1;
> cpsr.a = cpsr.a | abortDisable();
> cpsr.f = cpsr.f | fiqDisable();
> cpsr.i = 1;
> tc->setMiscReg(MISCREG_CPSR, cpsr);
> tc->setIntReg(INTREG_LR, tc->readPC() +
> (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
257,268c107,130
< void TrapFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< // warn("%s encountered.\n", name());
< setExceptionState(tc,0xD);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
---
> switch (nextMode()) {
> case MODE_FIQ:
> tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
> break;
> case MODE_IRQ:
> tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
> break;
> case MODE_SVC:
> tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
> break;
> case MODE_UNDEFINED:
> tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
> break;
> case MODE_ABORT:
> tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
> break;
> default:
> panic("unknown Mode\n");
> }
>
> DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr,
> tc->readPC(), tc->readIntReg(INTREG_LR));
> tc->setPC(getVector(tc));
> tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 );
270,449d131
<
< void BreakpointFault::invoke(ThreadContext *tc)
< {
< setExceptionState(tc,0x9);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
<
< }
<
< void DtbInvalidFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< // warn("%s encountered.\n", name());
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
< setExceptionState(tc,0x3);
<
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
< }
<
< void AddressErrorFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x4);
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< }
<
< void ItbInvalidFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x2);
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< DPRINTF(Arm,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
< }
<
< void ItbRefillFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered (%x).\n", name(),BadVAddr);
< Addr HandlerBase;
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< // Since handler depends on EXL bit, must check EXL bit before setting it!!
< if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< }else{
< HandlerBase = tc->readMiscReg(ArmISA::EBase); // Offset 0x000
< }
<
< setExceptionState(tc,0x2);
< setHandlerPC(HandlerBase,tc);
< }
<
< void DtbRefillFault::invoke(ThreadContext *tc)
< {
< // Set new PC
< DPRINTF(Arm,"%s encountered.\n", name());
< Addr HandlerBase;
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
< MiscReg stat = tc->readMiscReg(ArmISA::Status);
< // Since handler depends on EXL bit, must check EXL bit before setting it!!
< if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< }else{
< HandlerBase = tc->readMiscReg(ArmISA::EBase); // Offset 0x000
< }
<
<
< setExceptionState(tc,0x3);
<
< setHandlerPC(HandlerBase,tc);
< }
<
< void TLBModifiedFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
< MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
< replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
< replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
< replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
< tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
< MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
< replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
< tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setExceptionState(tc,0x1);
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
<
< }
<
< void SystemCallFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x8);
<
< // Set new PC
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< // warn("Exception Handler At: %x \n",HandlerBase);
< // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
<
< }
<
< void InterruptFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x0A);
< Addr HandlerBase;
<
<
< uint8_t IV = bits(tc->readMiscRegNoEffect(ArmISA::Cause),Cause_IV);
< if (IV)// Offset 200 for release 2
< HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(ArmISA::EBase);
< else//Ofset at 180 for release 1
< HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase);
<
< setHandlerPC(HandlerBase,tc);
< #endif
< }
<
452,461c134
< void ResetFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< /* All reset activity must be invoked from here */
< tc->setPC(vect());
< tc->setNextPC(vect()+sizeof(MachInst));
< tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
< DPRINTF(Arm,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
< #endif
---
> // return via SUBS pc, lr, xxx; rfe, movs, ldm
463,465d135
< // Set Coprocessor 1 (Floating Point) To Usable
< //tc->setMiscReg(ArmISA::Status, ArmISA::Status | 0x20000000);
< }
467,478d136
< void ReservedInstructionFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0x0A);
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
< #else
< panic("%s encountered.\n", name());
< #endif
< }
480,511d137
< void ThreadFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< panic("%s encountered.\n", name());
< }
<
< void DspStateDisabledFault::invoke(ThreadContext *tc)
< {
< DPRINTF(Arm,"%s encountered.\n", name());
< panic("%s encountered.\n", name());
< }
<
< void CoprocessorUnusableFault::invoke(ThreadContext *tc)
< {
< #if FULL_SYSTEM
< DPRINTF(Arm,"%s encountered.\n", name());
< setExceptionState(tc,0xb);
< /* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */
< MiscReg cause = tc->readMiscReg(ArmISA::Cause);
< replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID);
< tc->setMiscRegNoEffect(ArmISA::Cause,cause);
<
< Addr HandlerBase;
< HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
< setHandlerPC(HandlerBase,tc);
<
< // warn("Status: %x, Cause: %x\n",tc->readMiscReg(ArmISA::Status),tc->readMiscReg(ArmISA::Cause));
< #else
< warn("%s (CP%d) encountered.\n", name(), coProcID);
< #endif
< }
<