faults.cc (6735:6437ad24a8a0) | faults.cc (7093:9832d4b070fc) |
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1/* | 1/* |
2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; --- 80 unchanged lines hidden (view full) --- 90 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 91 tc->readIntReg(INTREG_CONDCODES); 92 93 94 cpsr.mode = nextMode(); 95 cpsr.it1 = cpsr.it2 = 0; 96 cpsr.j = 0; 97 | 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; --- 80 unchanged lines hidden (view full) --- 102 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 103 tc->readIntReg(INTREG_CONDCODES); 104 105 106 cpsr.mode = nextMode(); 107 cpsr.it1 = cpsr.it2 = 0; 108 cpsr.j = 0; 109 |
98 if (sctlr.te) 99 cpsr.t = 1; | 110 cpsr.t = sctlr.te; |
100 cpsr.a = cpsr.a | abortDisable(); 101 cpsr.f = cpsr.f | fiqDisable(); 102 cpsr.i = 1; 103 tc->setMiscReg(MISCREG_CPSR, cpsr); 104 tc->setIntReg(INTREG_LR, tc->readPC() + 105 (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 106 107 switch (nextMode()) { --- 9 unchanged lines hidden (view full) --- 117 case MODE_UNDEFINED: 118 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 119 break; 120 case MODE_ABORT: 121 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 122 break; 123 default: 124 panic("unknown Mode\n"); | 111 cpsr.a = cpsr.a | abortDisable(); 112 cpsr.f = cpsr.f | fiqDisable(); 113 cpsr.i = 1; 114 tc->setMiscReg(MISCREG_CPSR, cpsr); 115 tc->setIntReg(INTREG_LR, tc->readPC() + 116 (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 117 118 switch (nextMode()) { --- 9 unchanged lines hidden (view full) --- 128 case MODE_UNDEFINED: 129 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 130 break; 131 case MODE_ABORT: 132 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 133 break; 134 default: 135 panic("unknown Mode\n"); |
125 } 126 127 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr, 128 tc->readPC(), tc->readIntReg(INTREG_LR)); 129 tc->setPC(getVector(tc)); 130 tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 ); | 136 } 137 138 Addr pc = tc->readPC(); 139 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", 140 name(), cpsr, pc, tc->readIntReg(INTREG_LR)); 141 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0); 142 tc->setPC(newPc); 143 tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); |
131} 132#endif // FULL_SYSTEM 133 134// return via SUBS pc, lr, xxx; rfe, movs, ldm 135 136 137 138} // namespace ArmISA 139 | 144} 145#endif // FULL_SYSTEM 146 147// return via SUBS pc, lr, xxx; rfe, movs, ldm 148 149 150 151} // namespace ArmISA 152 |