1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA
53{
54
55template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
56{"reset", 0x00, MODE_SVC, 0, 0, true, true, FaultStat()};
57
58template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
59{"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false,
60 FaultStat()} ;
61
62template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
63{"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false, FaultStat()};
64
65template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
66{"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false, FaultStat()};
67
68template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
69{"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false, FaultStat()};
70
71template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
72{"IRQ", 0x18, MODE_IRQ, 4, 4, true, false, FaultStat()};
73
74template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
75{"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true, FaultStat()};
76
77template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
78{"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true, FaultStat()}; // dummy values
79
80template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals =
81{"ArmSev Flush", 0x00, MODE_SVC, 0, 0, true, true, FaultStat()}; // dummy values
82Addr
83ArmFault::getVector(ThreadContext *tc)
84{
85 // ARM ARM B1-3
86
87 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
88
89 // panic if SCTLR.VE because I have no idea what to do with vectored
90 // interrupts
91 assert(!sctlr.ve);
92
93 if (!sctlr.v)
94 return offset();
95 return offset() + HighVecs;
96
97}
98
99void
100ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
101{
102 // ARM ARM B1.6.3
103 FaultBase::invoke(tc);
104 if (!FullSystem)
105 return;
106 countStat()++;
107
108 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
109 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
110 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
111 saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
112 saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
113 saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
114 saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
115
116 Addr curPc M5_VAR_USED = tc->pcState().pc();
117 ITSTATE it = tc->pcState().itstate();
118 saved_cpsr.it2 = it.top6;
119 saved_cpsr.it1 = it.bottom2;
120
121 cpsr.mode = nextMode();
122 cpsr.it1 = cpsr.it2 = 0;
123 cpsr.j = 0;
124
125 cpsr.t = sctlr.te;
126 cpsr.a = cpsr.a | abortDisable();
127 cpsr.f = cpsr.f | fiqDisable();
128 cpsr.i = 1;
129 cpsr.e = sctlr.ee;
130 tc->setMiscReg(MISCREG_CPSR, cpsr);
131 // Make sure mailbox sets to one always
132 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
133 tc->setIntReg(INTREG_LR, curPc +
134 (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
135
136 switch (nextMode()) {
137 case MODE_FIQ:
138 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
139 break;
140 case MODE_IRQ:
141 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
142 break;
143 case MODE_SVC:
144 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
145 break;
146 case MODE_UNDEFINED:
147 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
148 break;
149 case MODE_ABORT:
150 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
151 break;
152 default:
153 panic("unknown Mode\n");
154 }
155
156 Addr newPc = getVector(tc);
157 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
158 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
159 PCState pc(newPc);
160 pc.thumb(cpsr.t);
161 pc.nextThumb(pc.thumb());
162 pc.jazelle(cpsr.j);
163 pc.nextJazelle(pc.jazelle());
164 tc->pcState(pc);
165}
166
167void
168Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
169{
170 if (FullSystem) {
171 tc->getCpuPtr()->clearInterrupts();
172 tc->clearArchRegs();
173 }
174 ArmFault::invoke(tc, inst);
175}
176
177void
178UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
179{
180 if (FullSystem) {
181 ArmFault::invoke(tc, inst);
182 return;

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191 panic("Attempted to execute unknown instruction (inst 0x%08x)",
192 machInst);
193 } else {
194 panic("Attempted to execute unimplemented instruction "
195 "'%s' (inst 0x%08x)", mnemonic, machInst);
196 }
197}
198
199void
200SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
201{
202 if (FullSystem) {
203 ArmFault::invoke(tc, inst);
204 return;
205 }
206
207 // As of now, there isn't a 32 bit thumb version of this instruction.
208 assert(!machInst.bigThumb);
209 uint32_t callNum;
210 callNum = tc->readIntReg(INTREG_R7);
211 tc->syscall(callNum);
212
213 // Advance the PC since that won't happen automatically.
214 PCState pc = tc->pcState();
215 assert(inst);
216 inst->advancePC(pc);
217 tc->pcState(pc);
218}
219
220template<class T>
221void
222AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
223{
224 ArmFaultVals<T>::invoke(tc, inst);
225 FSR fsr = 0;
226 fsr.fsLow = bits(status, 3, 0);
227 fsr.fsHigh = bits(status, 4);
228 fsr.domain = domain;
229 fsr.wnr = (write ? 1 : 0);
230 fsr.ext = 0;
231 tc->setMiscReg(T::FsrIndex, fsr);
232 tc->setMiscReg(T::FarIndex, faultAddr);
233
234 DPRINTF(Faults, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr, faultAddr);
235}
236
237void
238FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
239 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
240
241 // Set the PC to the next instruction of the faulting instruction.
242 // Net effect is simply squashing all instructions behind and
243 // start refetching from the next instruction.
244 PCState pc = tc->pcState();
245 assert(inst);
246 inst->advancePC(pc);
247 tc->pcState(pc);
248}
249
250template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
251 StaticInstPtr inst);
252template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
253 StaticInstPtr inst);
254
255void
256ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
257 DPRINTF(Faults, "Invoking ArmSev Fault\n");
258 if (!FullSystem)
259 return;
260
261 // Set sev_mailbox to 1, clear the pending interrupt from remote
262 // SEV execution and let pipeline continue as pcState is still
263 // valid.
264 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
265 tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
266}
267
268// return via SUBS pc, lr, xxx; rfe, movs, ldm
269
270} // namespace ArmISA