1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 39 unchanged lines hidden (view full) ---

48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA
53{
54
55template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
56 {"reset", 0x00, MODE_SVC, 0, 0, true, true};
57
58template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
59 {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
60
61template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
62 {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
63
64template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
65 {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
66
67template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
68 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
69
70template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
71 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
72
73template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
74 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
75
76template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
77 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
78
79template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals =
80 {"ArmSev Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
81Addr
82ArmFault::getVector(ThreadContext *tc)
83{
84 // ARM ARM B1-3
85
86 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
87
88 // panic if SCTLR.VE because I have no idea what to do with vectored

--- 181 unchanged lines hidden ---