1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173 ArmFault::invoke(tc, inst);
174}
175
176void
177UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
178{
179 if (FullSystem) {
180 ArmFault::invoke(tc, inst);
181 } else {
182 // If the mnemonic isn't defined this has to be an unknown instruction.
183 assert(unknown || mnemonic != NULL);
184 if (disabled) {
185 panic("Attempted to execute disabled instruction "
186 "'%s' (inst 0x%08x)", mnemonic, machInst);
187 } else if (unknown) {
188 panic("Attempted to execute unknown instruction (inst 0x%08x)",
189 machInst);
190 } else {
191 panic("Attempted to execute unimplemented instruction "
192 "'%s' (inst 0x%08x)", mnemonic, machInst);
193 }
194 }
195}
196
197void
198SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
199{
200 if (FullSystem) {
201 ArmFault::invoke(tc, inst);
202 } else {
203 // As of now, there isn't a 32 bit thumb version of this instruction.
204 assert(!machInst.bigThumb);
205 uint32_t callNum;
206 callNum = tc->readIntReg(INTREG_R7);
207 tc->syscall(callNum);
208
209 // Advance the PC since that won't happen automatically.
210 PCState pc = tc->pcState();
211 assert(inst);
212 inst->advancePC(pc);
213 tc->pcState(pc);
214 }
215}
216
217template<class T>
218void
219AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
220{
221 ArmFaultVals<T>::invoke(tc, inst);
222 FSR fsr = 0;

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247template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
248 StaticInstPtr inst);
249template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
250 StaticInstPtr inst);
251
252void
253ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
254 DPRINTF(Faults, "Invoking ArmSev Fault\n");
255 if (FullSystem) {
256 // Set sev_mailbox to 1, clear the pending interrupt from remote
257 // SEV execution and let pipeline continue as pcState is still
258 // valid.
259 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
260 tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
261 }
262}
263
264// return via SUBS pc, lr, xxx; rfe, movs, ldm
265
266} // namespace ArmISA