1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
70
71template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
73
74template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
75 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
76
77Addr
78ArmFault::getVector(ThreadContext *tc)
79{
80 // ARM ARM B1-3
81
82 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
83
84 // panic if SCTLR.VE because I have no idea what to do with vectored

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220 // start refetching from the next instruction.
221 PCState pc = tc->pcState();
222 assert(inst);
223 pc.forcedItState(inst->machInst.newItstate);
224 inst->advancePC(pc);
225 tc->pcState(pc);
226}
227
228template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
229 StaticInstPtr inst);
230template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
231 StaticInstPtr inst);
232
233// return via SUBS pc, lr, xxx; rfe, movs, ldm
234
235} // namespace ArmISA