1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1211 ((source >= ArmFault::AccessFlagLL) &&
1212 (source < ArmFault::AccessFlagLL + 4)) ||
1213 ((source >= ArmFault::DomainLL) &&
1214 (source < ArmFault::DomainLL + 4)) ||
1215 ((source >= ArmFault::PermissionLL) &&
1216 (source < ArmFault::PermissionLL + 4));
1217}
1218
1219ExceptionClass
1220PrefetchAbort::ec(ThreadContext *tc) const
1221{
1222 if (to64) {
1223 // AArch64
1224 if (toEL == fromEL)
1225 return EC_PREFETCH_ABORT_CURR_EL;
1226 else

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1613template class AbortFault<PrefetchAbort>;
1614template class AbortFault<DataAbort>;
1615template class AbortFault<VirtualDataAbort>;
1616
1617
1618IllegalInstSetStateFault::IllegalInstSetStateFault()
1619{}
1620
1621
1622} // namespace ArmISA