1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173 ArmFault::invoke(tc, inst);
174}
175
176void
177UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
178{
179 if (FullSystem) {
180 ArmFault::invoke(tc, inst);
181 return;
182 }
183
184 // If the mnemonic isn't defined this has to be an unknown instruction.
185 assert(unknown || mnemonic != NULL);
186 if (disabled) {
187 panic("Attempted to execute disabled instruction "
188 "'%s' (inst 0x%08x)", mnemonic, machInst);
189 } else if (unknown) {
190 panic("Attempted to execute unknown instruction (inst 0x%08x)",
191 machInst);
192 } else {
193 panic("Attempted to execute unimplemented instruction "
194 "'%s' (inst 0x%08x)", mnemonic, machInst);
195 }
196}
197
198void
199SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
200{
201 if (FullSystem) {
202 ArmFault::invoke(tc, inst);
203 return;
204 }
205
206 // As of now, there isn't a 32 bit thumb version of this instruction.
207 assert(!machInst.bigThumb);
208 uint32_t callNum;
209 callNum = tc->readIntReg(INTREG_R7);
210 tc->syscall(callNum);
211
212 // Advance the PC since that won't happen automatically.
213 PCState pc = tc->pcState();
214 assert(inst);
215 inst->advancePC(pc);
216 tc->pcState(pc);
217}
218
219template<class T>
220void
221AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
222{
223 ArmFaultVals<T>::invoke(tc, inst);
224 FSR fsr = 0;

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249template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
250 StaticInstPtr inst);
251template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
252 StaticInstPtr inst);
253
254void
255ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
256 DPRINTF(Faults, "Invoking ArmSev Fault\n");
257 if (!FullSystem)
258 return;
259
260 // Set sev_mailbox to 1, clear the pending interrupt from remote
261 // SEV execution and let pipeline continue as pcState is still
262 // valid.
263 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
264 tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
265}
266
267// return via SUBS pc, lr, xxx; rfe, movs, ldm
268
269} // namespace ArmISA