1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45
46#include <cassert>
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "arch/generic/decode_cache.hh"
51#include "base/types.hh"
52#include "cpu/static_inst.hh"
53
54namespace ArmISA
55{
56
57class Decoder
58{
59 protected:
60 //The extended machine instruction being generated
61 ExtMachInst emi;
62 MachInst data;
63 bool bigThumb;
64 bool instDone;
65 bool outOfBytes;
66 int offset;
67 bool foundIt;
68 ITSTATE itBits;
69
70 int fpscrLen;
71 int fpscrStride;
72
73 /// A cache of decoded instruction objects.
74 static GenericISA::BasicDecodeCache defaultCache;
75
76 /**
77 * Pre-decode an instruction from the current state of the
78 * decoder.
79 */
80 void process();
81
82 /**
83 * Consume bytes by moving the offset into the data word and
84 * sanity check the results.
85 */
86 void consumeBytes(int numBytes);
87
88 public: // Decoder API
89 Decoder();
90
91 /** Reset the decoders internal state. */
92 void reset();
93
94 /**
95 * Can the decoder accept more data?
96 *
97 * A CPU model uses this method to determine if the decoder can

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