1/*
2 * Copyright (c) 2012-2014,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42
43#include "arch/arm/decoder.hh"
44
45#include "arch/arm/isa.hh"
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/utility.hh"
48#include "base/trace.hh"
49#include "debug/Decoder.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA
53{
54
55GenericISA::BasicDecodeCache Decoder::defaultCache;
56
57Decoder::Decoder(ISA* isa)
58 : data(0), fpscrLen(0), fpscrStride(0),
59 decoderFlavour(isa->decoderFlavour())
60{
61 reset();
62
63 // Initialize SVE vector length
64 sveLen = (isa->getCurSveVecLenInBitsAtReset() >> 7) - 1;
65}
66
67void
68Decoder::reset()
69{
70 bigThumb = false;
71 offset = 0;
72 emi = 0;

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155Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
156{
157 data = inst;
158 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
159 emi.thumb = pc.thumb();
160 emi.aarch64 = pc.aarch64();
161 emi.fpscrLen = fpscrLen;
162 emi.fpscrStride = fpscrStride;
163 emi.sveLen = sveLen;
164
165 const Addr alignment(pc.thumb() ? 0x1 : 0x3);
166 emi.decoderFault = static_cast<uint8_t>(
167 pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK);
168
169 outOfBytes = false;
170 process();
171}

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