SConscript (8777:dd43f1c9fa0a) SConscript (8782:10c9297e14d5)
1# -*- mode:python -*-
2
3# Copyright (c) 2009 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

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51 Source('insts/macromem.cc')
52 Source('insts/mem.cc')
53 Source('insts/misc.cc')
54 Source('insts/pred_inst.cc')
55 Source('insts/static_inst.cc')
56 Source('insts/vfp.cc')
57 Source('interrupts.cc')
58 Source('isa.cc')
1# -*- mode:python -*-
2
3# Copyright (c) 2009 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

--- 42 unchanged lines hidden (view full) ---

51 Source('insts/macromem.cc')
52 Source('insts/mem.cc')
53 Source('insts/misc.cc')
54 Source('insts/pred_inst.cc')
55 Source('insts/static_inst.cc')
56 Source('insts/vfp.cc')
57 Source('interrupts.cc')
58 Source('isa.cc')
59 Source('linux/linux.cc')
60 Source('linux/process.cc')
61 Source('linux/system.cc')
59 Source('miscregs.cc')
60 Source('nativetrace.cc')
61 Source('predecoder.cc')
62 Source('miscregs.cc')
63 Source('nativetrace.cc')
64 Source('predecoder.cc')
65 Source('process.cc')
62 Source('remote_gdb.cc')
63 Source('stacktrace.cc')
66 Source('remote_gdb.cc')
67 Source('stacktrace.cc')
68 Source('system.cc')
64 Source('table_walker.cc')
65 Source('tlb.cc')
66 Source('utility.cc')
67 Source('vtophys.cc')
68
69 SimObject('ArmInterrupts.py')
70 SimObject('ArmNativeTrace.py')
69 Source('table_walker.cc')
70 Source('tlb.cc')
71 Source('utility.cc')
72 Source('vtophys.cc')
73
74 SimObject('ArmInterrupts.py')
75 SimObject('ArmNativeTrace.py')
76 SimObject('ArmSystem.py')
71 SimObject('ArmTLB.py')
72
73 DebugFlag('Arm')
74 DebugFlag('TLBVerbose')
75 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
76 DebugFlag('Predecoder', "Instructions returned by the predecoder")
77 SimObject('ArmTLB.py')
78
79 DebugFlag('Arm')
80 DebugFlag('TLBVerbose')
81 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
82 DebugFlag('Predecoder', "Instructions returned by the predecoder")
77 if env['FULL_SYSTEM']:
78 Source('system.cc')
79 Source('linux/system.cc')
80
81 SimObject('ArmSystem.py')
82 else:
83 Source('process.cc')
84 Source('linux/linux.cc')
85 Source('linux/process.cc')
86
87 # Add in files generated by the ISA description.
88 isa_desc_files = env.ISADesc('isa/main.isa')
89 # Only non-header files need to be compiled.
90 for f in isa_desc_files:
91 if not f.path.endswith('.hh'):
92 Source(f)
93
83
84 # Add in files generated by the ISA description.
85 isa_desc_files = env.ISADesc('isa/main.isa')
86 # Only non-header files need to be compiled.
87 for f in isa_desc_files:
88 if not f.path.endswith('.hh'):
89 Source(f)
90