SConscript (8756:cce8cf3906ca) | SConscript (8757:3149b641eca8) |
---|---|
1# -*- mode:python -*- 2 3# Copyright (c) 2009 ARM Limited 4# All rights reserved. 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating --- 43 unchanged lines hidden (view full) --- 52 Source('insts/mem.cc') 53 Source('insts/misc.cc') 54 Source('insts/pred_inst.cc') 55 Source('insts/static_inst.cc') 56 Source('insts/vfp.cc') 57 Source('interrupts.cc') 58 Source('isa.cc') 59 Source('miscregs.cc') | 1# -*- mode:python -*- 2 3# Copyright (c) 2009 ARM Limited 4# All rights reserved. 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating --- 43 unchanged lines hidden (view full) --- 52 Source('insts/mem.cc') 53 Source('insts/misc.cc') 54 Source('insts/pred_inst.cc') 55 Source('insts/static_inst.cc') 56 Source('insts/vfp.cc') 57 Source('interrupts.cc') 58 Source('isa.cc') 59 Source('miscregs.cc') |
60 Source('predecoder.cc') | |
61 Source('nativetrace.cc') | 60 Source('nativetrace.cc') |
61 Source('predecoder.cc') 62 Source('remote_gdb.cc') |
|
62 Source('table_walker.cc') 63 Source('tlb.cc') 64 Source('utility.cc') | 63 Source('table_walker.cc') 64 Source('tlb.cc') 65 Source('utility.cc') |
65 Source('remote_gdb.cc') | 66 Source('vtophys.cc') |
66 67 SimObject('ArmInterrupts.py') 68 SimObject('ArmNativeTrace.py') 69 SimObject('ArmTLB.py') 70 71 DebugFlag('Arm') 72 DebugFlag('TLBVerbose') 73 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") 74 DebugFlag('Predecoder', "Instructions returned by the predecoder") 75 if env['FULL_SYSTEM']: 76 Source('stacktrace.cc') 77 Source('system.cc') | 67 68 SimObject('ArmInterrupts.py') 69 SimObject('ArmNativeTrace.py') 70 SimObject('ArmTLB.py') 71 72 DebugFlag('Arm') 73 DebugFlag('TLBVerbose') 74 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") 75 DebugFlag('Predecoder', "Instructions returned by the predecoder") 76 if env['FULL_SYSTEM']: 77 Source('stacktrace.cc') 78 Source('system.cc') |
78 Source('vtophys.cc') | |
79 Source('linux/system.cc') 80 81 SimObject('ArmSystem.py') 82 else: 83 Source('process.cc') 84 Source('linux/linux.cc') 85 Source('linux/process.cc') 86 87 # Add in files generated by the ISA description. 88 isa_desc_files = env.ISADesc('isa/main.isa') 89 # Only non-header files need to be compiled. 90 for f in isa_desc_files: 91 if not f.path.endswith('.hh'): 92 Source(f) 93 | 79 Source('linux/system.cc') 80 81 SimObject('ArmSystem.py') 82 else: 83 Source('process.cc') 84 Source('linux/linux.cc') 85 Source('linux/process.cc') 86 87 # Add in files generated by the ISA description. 88 isa_desc_files = env.ISADesc('isa/main.isa') 89 # Only non-header files need to be compiled. 90 for f in isa_desc_files: 91 if not f.path.endswith('.hh'): 92 Source(f) 93 |