SConscript (8335:9228e00459d4) SConscript (8745:575cab0db076)
1# -*- mode:python -*-
2
3# Copyright (c) 2009 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

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49 Dir('isa/formats')
50 Source('faults.cc')
51 Source('insts/macromem.cc')
52 Source('insts/mem.cc')
53 Source('insts/misc.cc')
54 Source('insts/pred_inst.cc')
55 Source('insts/static_inst.cc')
56 Source('insts/vfp.cc')
1# -*- mode:python -*-
2
3# Copyright (c) 2009 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

--- 40 unchanged lines hidden (view full) ---

49 Dir('isa/formats')
50 Source('faults.cc')
51 Source('insts/macromem.cc')
52 Source('insts/mem.cc')
53 Source('insts/misc.cc')
54 Source('insts/pred_inst.cc')
55 Source('insts/static_inst.cc')
56 Source('insts/vfp.cc')
57 Source('interrupts.cc')
57 Source('isa.cc')
58 Source('miscregs.cc')
59 Source('predecoder.cc')
60 Source('nativetrace.cc')
61 Source('tlb.cc')
62 Source('utility.cc')
63 Source('remote_gdb.cc')
64
58 Source('isa.cc')
59 Source('miscregs.cc')
60 Source('predecoder.cc')
61 Source('nativetrace.cc')
62 Source('tlb.cc')
63 Source('utility.cc')
64 Source('remote_gdb.cc')
65
66 SimObject('ArmInterrupts.py')
65 SimObject('ArmNativeTrace.py')
66 SimObject('ArmTLB.py')
67
68 DebugFlag('Arm')
69 DebugFlag('TLBVerbose')
70 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
71 DebugFlag('Predecoder', "Instructions returned by the predecoder")
72 if env['FULL_SYSTEM']:
67 SimObject('ArmNativeTrace.py')
68 SimObject('ArmTLB.py')
69
70 DebugFlag('Arm')
71 DebugFlag('TLBVerbose')
72 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
73 DebugFlag('Predecoder', "Instructions returned by the predecoder")
74 if env['FULL_SYSTEM']:
73 Source('interrupts.cc')
74 Source('stacktrace.cc')
75 Source('system.cc')
76 Source('vtophys.cc')
77 Source('linux/system.cc')
78 Source('table_walker.cc')
79
75 Source('stacktrace.cc')
76 Source('system.cc')
77 Source('vtophys.cc')
78 Source('linux/system.cc')
79 Source('table_walker.cc')
80
80 SimObject('ArmInterrupts.py')
81 SimObject('ArmSystem.py')
82 else:
83 Source('process.cc')
84 Source('linux/linux.cc')
85 Source('linux/process.cc')
86
87 # Add in files generated by the ISA description.
88 isa_desc_files = env.ISADesc('isa/main.isa')
89 # Only non-header files need to be compiled.
90 for f in isa_desc_files:
91 if not f.path.endswith('.hh'):
92 Source(f)
93
81 SimObject('ArmSystem.py')
82 else:
83 Source('process.cc')
84 Source('linux/linux.cc')
85 Source('linux/process.cc')
86
87 # Add in files generated by the ISA description.
88 isa_desc_files = env.ISADesc('isa/main.isa')
89 # Only non-header files need to be compiled.
90 for f in isa_desc_files:
91 if not f.path.endswith('.hh'):
92 Source(f)
93