SConscript (12222:6db0fc7407a5) | SConscript (12531:3141027bd11a) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2009, 2012-2013 ARM Limited 4# All rights reserved. 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating --- 61 unchanged lines hidden (view full) --- 70 Source('freebsd/freebsd.cc') 71 Source('freebsd/process.cc') 72 Source('freebsd/system.cc') 73 Source('miscregs.cc') 74 Source('nativetrace.cc') 75 Source('pmu.cc') 76 Source('process.cc') 77 Source('remote_gdb.cc') | 1# -*- mode:python -*- 2 3# Copyright (c) 2009, 2012-2013 ARM Limited 4# All rights reserved. 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating --- 61 unchanged lines hidden (view full) --- 70 Source('freebsd/freebsd.cc') 71 Source('freebsd/process.cc') 72 Source('freebsd/system.cc') 73 Source('miscregs.cc') 74 Source('nativetrace.cc') 75 Source('pmu.cc') 76 Source('process.cc') 77 Source('remote_gdb.cc') |
78 Source('semihosting.cc') |
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78 Source('stacktrace.cc') 79 Source('system.cc') 80 Source('table_walker.cc') 81 Source('stage2_mmu.cc') 82 Source('stage2_lookup.cc') 83 Source('tlb.cc') 84 Source('utility.cc') 85 Source('vtophys.cc') 86 87 SimObject('ArmInterrupts.py') 88 SimObject('ArmISA.py') 89 SimObject('ArmNativeTrace.py') | 79 Source('stacktrace.cc') 80 Source('system.cc') 81 Source('table_walker.cc') 82 Source('stage2_mmu.cc') 83 Source('stage2_lookup.cc') 84 Source('tlb.cc') 85 Source('utility.cc') 86 Source('vtophys.cc') 87 88 SimObject('ArmInterrupts.py') 89 SimObject('ArmISA.py') 90 SimObject('ArmNativeTrace.py') |
91 SimObject('ArmSemihosting.py') |
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90 SimObject('ArmSystem.py') 91 SimObject('ArmTLB.py') 92 SimObject('ArmPMU.py') 93 94 DebugFlag('Arm') | 92 SimObject('ArmSystem.py') 93 SimObject('ArmTLB.py') 94 SimObject('ArmPMU.py') 95 96 DebugFlag('Arm') |
97 DebugFlag('Semihosting') |
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95 DebugFlag('Decoder', "Instructions returned by the predecoder") 96 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") 97 DebugFlag('PMUVerbose', "Performance Monitor") 98 DebugFlag('TLBVerbose') 99 100 # Add files generated by the ISA description. 101 ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6) | 98 DebugFlag('Decoder', "Instructions returned by the predecoder") 99 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") 100 DebugFlag('PMUVerbose', "Performance Monitor") 101 DebugFlag('TLBVerbose') 102 103 # Add files generated by the ISA description. 104 ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6) |