SConscript (10196:be0e1724eb39) SConscript (10461:afeb5cdb3907)
1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2012-2013 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

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57 Source('insts/misc.cc')
58 Source('insts/misc64.cc')
59 Source('insts/pred_inst.cc')
60 Source('insts/static_inst.cc')
61 Source('insts/vfp.cc')
62 Source('insts/fplib.cc')
63 Source('interrupts.cc')
64 Source('isa.cc')
1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2012-2013 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

--- 48 unchanged lines hidden (view full) ---

57 Source('insts/misc.cc')
58 Source('insts/misc64.cc')
59 Source('insts/pred_inst.cc')
60 Source('insts/static_inst.cc')
61 Source('insts/vfp.cc')
62 Source('insts/fplib.cc')
63 Source('interrupts.cc')
64 Source('isa.cc')
65 Source('isa_device.cc')
65 Source('linux/linux.cc')
66 Source('linux/process.cc')
67 Source('linux/system.cc')
68 Source('miscregs.cc')
69 Source('nativetrace.cc')
66 Source('linux/linux.cc')
67 Source('linux/process.cc')
68 Source('linux/system.cc')
69 Source('miscregs.cc')
70 Source('nativetrace.cc')
71 Source('pmu.cc')
70 Source('process.cc')
71 Source('remote_gdb.cc')
72 Source('stacktrace.cc')
73 Source('system.cc')
74 Source('table_walker.cc')
75 Source('stage2_mmu.cc')
76 Source('stage2_lookup.cc')
77 Source('tlb.cc')
78 Source('utility.cc')
79 Source('vtophys.cc')
80
81 SimObject('ArmInterrupts.py')
82 SimObject('ArmISA.py')
83 SimObject('ArmNativeTrace.py')
84 SimObject('ArmSystem.py')
85 SimObject('ArmTLB.py')
72 Source('process.cc')
73 Source('remote_gdb.cc')
74 Source('stacktrace.cc')
75 Source('system.cc')
76 Source('table_walker.cc')
77 Source('stage2_mmu.cc')
78 Source('stage2_lookup.cc')
79 Source('tlb.cc')
80 Source('utility.cc')
81 Source('vtophys.cc')
82
83 SimObject('ArmInterrupts.py')
84 SimObject('ArmISA.py')
85 SimObject('ArmNativeTrace.py')
86 SimObject('ArmSystem.py')
87 SimObject('ArmTLB.py')
88 SimObject('ArmPMU.py')
86
87 DebugFlag('Arm')
88 DebugFlag('Decoder', "Instructions returned by the predecoder")
89 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
89
90 DebugFlag('Arm')
91 DebugFlag('Decoder', "Instructions returned by the predecoder")
92 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
93 DebugFlag('PMUVerbose', "Performance Monitor")
90 DebugFlag('TLBVerbose')
91
92 # Add files generated by the ISA description.
93 env.ISADesc('isa/main.isa')
94 DebugFlag('TLBVerbose')
95
96 # Add files generated by the ISA description.
97 env.ISADesc('isa/main.isa')