1# -*- mode:python -*-
2
3# Copyright (c) 2009 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder. You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Copyright (c) 2007-2008 The Florida State University
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Stephen Hines
42# Ali Saidi
43
44Import('*')
45
46if env['TARGET_ISA'] == 'arm':
47# Workaround for bug in SCons version > 0.97d20071212
48# Scons bug id: 2006 M5 Bug id: 308
49 Dir('isa/formats')
50 Source('decoder.cc')
51 Source('faults.cc')
52 Source('insts/macromem.cc')
53 Source('insts/mem.cc')
54 Source('insts/misc.cc')
55 Source('insts/pred_inst.cc')
56 Source('insts/static_inst.cc')
57 Source('insts/vfp.cc')
58 Source('interrupts.cc')
59 Source('isa.cc')
60 Source('linux/linux.cc')
61 Source('linux/process.cc')
62 Source('linux/system.cc')
63 Source('miscregs.cc')
64 Source('nativetrace.cc')
65 Source('process.cc')
66 Source('remote_gdb.cc')
67 Source('stacktrace.cc')
68 Source('system.cc')
69 Source('table_walker.cc')
70 Source('tlb.cc')
71 Source('utility.cc')
72 Source('vtophys.cc')
73
74 SimObject('ArmInterrupts.py')
| 1# -*- mode:python -*-
2
3# Copyright (c) 2009 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder. You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Copyright (c) 2007-2008 The Florida State University
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Stephen Hines
42# Ali Saidi
43
44Import('*')
45
46if env['TARGET_ISA'] == 'arm':
47# Workaround for bug in SCons version > 0.97d20071212
48# Scons bug id: 2006 M5 Bug id: 308
49 Dir('isa/formats')
50 Source('decoder.cc')
51 Source('faults.cc')
52 Source('insts/macromem.cc')
53 Source('insts/mem.cc')
54 Source('insts/misc.cc')
55 Source('insts/pred_inst.cc')
56 Source('insts/static_inst.cc')
57 Source('insts/vfp.cc')
58 Source('interrupts.cc')
59 Source('isa.cc')
60 Source('linux/linux.cc')
61 Source('linux/process.cc')
62 Source('linux/system.cc')
63 Source('miscregs.cc')
64 Source('nativetrace.cc')
65 Source('process.cc')
66 Source('remote_gdb.cc')
67 Source('stacktrace.cc')
68 Source('system.cc')
69 Source('table_walker.cc')
70 Source('tlb.cc')
71 Source('utility.cc')
72 Source('vtophys.cc')
73
74 SimObject('ArmInterrupts.py')
|
75 SimObject('ArmNativeTrace.py')
76 SimObject('ArmSystem.py')
77 SimObject('ArmTLB.py')
78
79 DebugFlag('Arm')
80 DebugFlag('Decoder', "Instructions returned by the predecoder")
81 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
82 DebugFlag('TLBVerbose')
83
84 # Add in files generated by the ISA description.
85 isa_desc_files = env.ISADesc('isa/main.isa')
86 # Only non-header files need to be compiled.
87 for f in isa_desc_files:
88 if not f.path.endswith('.hh'):
89 Source(f)
90
| 76 SimObject('ArmNativeTrace.py')
77 SimObject('ArmSystem.py')
78 SimObject('ArmTLB.py')
79
80 DebugFlag('Arm')
81 DebugFlag('Decoder', "Instructions returned by the predecoder")
82 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
83 DebugFlag('TLBVerbose')
84
85 # Add in files generated by the ISA description.
86 isa_desc_files = env.ISADesc('isa/main.isa')
87 # Only non-header files need to be compiled.
88 for f in isa_desc_files:
89 if not f.path.endswith('.hh'):
90 Source(f)
91
|