ArmTLB.py (12005:f4b9607db0af) ArmTLB.py (12433:b166ca57bf0e)
1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2013, 2015 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

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36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37#
38# Authors: Ali Saidi
39
40from m5.SimObject import SimObject
41from m5.params import *
42from m5.proxy import *
43from MemObject import MemObject
1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2013, 2015 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating

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36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37#
38# Authors: Ali Saidi
39
40from m5.SimObject import SimObject
41from m5.params import *
42from m5.proxy import *
43from MemObject import MemObject
44from BaseTLB import BaseTLB
44
45# Basic stage 1 translation objects
46class ArmTableWalker(MemObject):
47 type = 'ArmTableWalker'
48 cxx_class = 'ArmISA::TableWalker'
49 cxx_header = "arch/arm/table_walker.hh"
50 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
51 num_squash_per_cycle = Param.Unsigned(2,
52 "Number of outstanding walks that can be squashed per cycle")
53
54 # The port to the memory system. This port is ultimately belonging
55 # to the Stage2MMU, and shared by the two table walkers, but we
56 # access it through the ITB and DTB walked objects in the CPU for
57 # symmetry with the other ISAs.
58 port = MasterPort("Port used by the two table walkers")
59
60 sys = Param.System(Parent.any, "system object parameter")
61
45
46# Basic stage 1 translation objects
47class ArmTableWalker(MemObject):
48 type = 'ArmTableWalker'
49 cxx_class = 'ArmISA::TableWalker'
50 cxx_header = "arch/arm/table_walker.hh"
51 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
52 num_squash_per_cycle = Param.Unsigned(2,
53 "Number of outstanding walks that can be squashed per cycle")
54
55 # The port to the memory system. This port is ultimately belonging
56 # to the Stage2MMU, and shared by the two table walkers, but we
57 # access it through the ITB and DTB walked objects in the CPU for
58 # symmetry with the other ISAs.
59 port = MasterPort("Port used by the two table walkers")
60
61 sys = Param.System(Parent.any, "system object parameter")
62
62class ArmTLB(SimObject):
63class ArmTLB(BaseTLB):
63 type = 'ArmTLB'
64 cxx_class = 'ArmISA::TLB'
65 cxx_header = "arch/arm/tlb.hh"
66 sys = Param.System(Parent.any, "system object parameter")
67 size = Param.Int(64, "TLB size")
68 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
69 is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
70

--- 29 unchanged lines hidden --- 		64 type = 'ArmTLB'
65 cxx_class = 'ArmISA::TLB'
66 cxx_header = "arch/arm/tlb.hh"
67 sys = Param.System(Parent.any, "system object parameter")
68 size = Param.Int(64, "TLB size")
69 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
70 is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
71

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