1# -*- mode:python -*- 2 3# Copyright (c) 2009, 2013, 2015 ARM Limited 4# All rights reserved. 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating --- 26 unchanged lines hidden (view full) --- 35# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37# 38# Authors: Ali Saidi 39 40from m5.SimObject import SimObject 41from m5.params import * 42from m5.proxy import * |
43from m5.objects.BaseTLB import BaseTLB |
44from m5.objects.ClockedObject import ClockedObject |
45 46# Basic stage 1 translation objects |
47class ArmTableWalker(ClockedObject): |
48 type = 'ArmTableWalker' 49 cxx_class = 'ArmISA::TableWalker' 50 cxx_header = "arch/arm/table_walker.hh" 51 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?") 52 num_squash_per_cycle = Param.Unsigned(2, 53 "Number of outstanding walks that can be squashed per cycle") 54 55 # The port to the memory system. This port is ultimately belonging --- 45 unchanged lines hidden --- |