1# -*- mode:python -*- 2 |
3# Copyright (c) 2009, 2013, 2015 ARM Limited |
4# All rights reserved. 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating 9# to a hardware implementation of the functionality of the software 10# licensed hereunder. You may use the software subject to the license 11# terms below provided that you ensure that this notice is replicated --- 31 unchanged lines hidden (view full) --- 43from MemObject import MemObject 44 45# Basic stage 1 translation objects 46class ArmTableWalker(MemObject): 47 type = 'ArmTableWalker' 48 cxx_class = 'ArmISA::TableWalker' 49 cxx_header = "arch/arm/table_walker.hh" 50 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?") |
51 num_squash_per_cycle = Param.Unsigned(2, 52 "Number of outstanding walks that can be squashed per cycle") 53 |
54 # The port to the memory system. This port is ultimately belonging 55 # to the Stage2MMU, and shared by the two table walkers, but we 56 # access it through the ITB and DTB walked objects in the CPU for 57 # symmetry with the other ISAs. 58 port = MasterPort("Port used by the two table walkers") 59 60 sys = Param.System(Parent.any, "system object parameter") 61 |
62class ArmTLB(SimObject): 63 type = 'ArmTLB' 64 cxx_class = 'ArmISA::TLB' 65 cxx_header = "arch/arm/tlb.hh" 66 size = Param.Int(64, "TLB size") 67 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") 68 is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?") 69 --- 8 unchanged lines hidden (view full) --- 78 79class ArmStage2MMU(SimObject): 80 type = 'ArmStage2MMU' 81 cxx_class = 'ArmISA::Stage2MMU' 82 cxx_header = 'arch/arm/stage2_mmu.hh' 83 tlb = Param.ArmTLB("Stage 1 TLB") 84 stage2_tlb = Param.ArmTLB("Stage 2 TLB") 85 |
86 sys = Param.System(Parent.any, "system object parameter") 87 |
88class ArmStage2IMMU(ArmStage2MMU): |
89 # We rely on the itb being a parameter of the CPU, and get the 90 # appropriate object that way |
91 tlb = Parent.itb |
92 stage2_tlb = ArmStage2TLB() |
93 94class ArmStage2DMMU(ArmStage2MMU): |
95 # We rely on the dtb being a parameter of the CPU, and get the 96 # appropriate object that way |
97 tlb = Parent.dtb |
98 stage2_tlb = ArmStage2TLB() |