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< # Copyright (c) 2009, 2013 ARM Limited
---
> # Copyright (c) 2009, 2013, 2015 ARM Limited
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< port = MasterPort("Port for TableWalker to do walk the translation with")
< sys = Param.System(Parent.any, "system object parameter")
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> # The port to the memory system. This port is ultimately belonging
> # to the Stage2MMU, and shared by the two table walkers, but we
> # access it through the ITB and DTB walked objects in the CPU for
> # symmetry with the other ISAs.
> port = MasterPort("Port used by the two table walkers")
>
> sys = Param.System(Parent.any, "system object parameter")
>
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> sys = Param.System(Parent.any, "system object parameter")
>
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> # We rely on the itb being a parameter of the CPU, and get the
> # appropriate object that way
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< stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
---
> stage2_tlb = ArmStage2TLB()
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> # We rely on the dtb being a parameter of the CPU, and get the
> # appropriate object that way
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< stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
---
> stage2_tlb = ArmStage2TLB()