1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2013, 2015 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder. You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Redistribution and use in source and binary forms, with or without
16# modification, are permitted provided that the following conditions are
17# met: redistributions of source code must retain the above copyright
18# notice, this list of conditions and the following disclaimer;
19# redistributions in binary form must reproduce the above copyright
20# notice, this list of conditions and the following disclaimer in the
21# documentation and/or other materials provided with the distribution;
22# neither the name of the copyright holders nor the names of its
23# contributors may be used to endorse or promote products derived from
24# this software without specific prior written permission.
25#
26# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37#
38# Authors: Ali Saidi
39
40from m5.SimObject import SimObject
41from m5.params import *
42from m5.proxy import *
43from MemObject import MemObject
44
45# Basic stage 1 translation objects
46class ArmTableWalker(MemObject):
47 type = 'ArmTableWalker'
48 cxx_class = 'ArmISA::TableWalker'
49 cxx_header = "arch/arm/table_walker.hh"
50 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
51 num_squash_per_cycle = Param.Unsigned(2,
52 "Number of outstanding walks that can be squashed per cycle")
53
54 # The port to the memory system. This port is ultimately belonging
55 # to the Stage2MMU, and shared by the two table walkers, but we
56 # access it through the ITB and DTB walked objects in the CPU for
57 # symmetry with the other ISAs.
58 port = MasterPort("Port used by the two table walkers")
59
60 sys = Param.System(Parent.any, "system object parameter")
61
62class ArmTLB(SimObject):
63 type = 'ArmTLB'
64 cxx_class = 'ArmISA::TLB'
65 cxx_header = "arch/arm/tlb.hh"
| 1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2013, 2015 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder. You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Redistribution and use in source and binary forms, with or without
16# modification, are permitted provided that the following conditions are
17# met: redistributions of source code must retain the above copyright
18# notice, this list of conditions and the following disclaimer;
19# redistributions in binary form must reproduce the above copyright
20# notice, this list of conditions and the following disclaimer in the
21# documentation and/or other materials provided with the distribution;
22# neither the name of the copyright holders nor the names of its
23# contributors may be used to endorse or promote products derived from
24# this software without specific prior written permission.
25#
26# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37#
38# Authors: Ali Saidi
39
40from m5.SimObject import SimObject
41from m5.params import *
42from m5.proxy import *
43from MemObject import MemObject
44
45# Basic stage 1 translation objects
46class ArmTableWalker(MemObject):
47 type = 'ArmTableWalker'
48 cxx_class = 'ArmISA::TableWalker'
49 cxx_header = "arch/arm/table_walker.hh"
50 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
51 num_squash_per_cycle = Param.Unsigned(2,
52 "Number of outstanding walks that can be squashed per cycle")
53
54 # The port to the memory system. This port is ultimately belonging
55 # to the Stage2MMU, and shared by the two table walkers, but we
56 # access it through the ITB and DTB walked objects in the CPU for
57 # symmetry with the other ISAs.
58 port = MasterPort("Port used by the two table walkers")
59
60 sys = Param.System(Parent.any, "system object parameter")
61
62class ArmTLB(SimObject):
63 type = 'ArmTLB'
64 cxx_class = 'ArmISA::TLB'
65 cxx_header = "arch/arm/tlb.hh"
|
66 size = Param.Int(64, "TLB size")
67 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
68 is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
69
70# Stage 2 translation objects, only used when virtualisation is being used
71class ArmStage2TableWalker(ArmTableWalker):
72 is_stage2 = True
73
74class ArmStage2TLB(ArmTLB):
75 size = 32
76 walker = ArmStage2TableWalker()
77 is_stage2 = True
78
79class ArmStage2MMU(SimObject):
80 type = 'ArmStage2MMU'
81 cxx_class = 'ArmISA::Stage2MMU'
82 cxx_header = 'arch/arm/stage2_mmu.hh'
83 tlb = Param.ArmTLB("Stage 1 TLB")
84 stage2_tlb = Param.ArmTLB("Stage 2 TLB")
85
86 sys = Param.System(Parent.any, "system object parameter")
87
88class ArmStage2IMMU(ArmStage2MMU):
89 # We rely on the itb being a parameter of the CPU, and get the
90 # appropriate object that way
91 tlb = Parent.itb
92 stage2_tlb = ArmStage2TLB()
93
94class ArmStage2DMMU(ArmStage2MMU):
95 # We rely on the dtb being a parameter of the CPU, and get the
96 # appropriate object that way
97 tlb = Parent.dtb
98 stage2_tlb = ArmStage2TLB()
| 67 size = Param.Int(64, "TLB size")
68 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
69 is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
70
71# Stage 2 translation objects, only used when virtualisation is being used
72class ArmStage2TableWalker(ArmTableWalker):
73 is_stage2 = True
74
75class ArmStage2TLB(ArmTLB):
76 size = 32
77 walker = ArmStage2TableWalker()
78 is_stage2 = True
79
80class ArmStage2MMU(SimObject):
81 type = 'ArmStage2MMU'
82 cxx_class = 'ArmISA::Stage2MMU'
83 cxx_header = 'arch/arm/stage2_mmu.hh'
84 tlb = Param.ArmTLB("Stage 1 TLB")
85 stage2_tlb = Param.ArmTLB("Stage 2 TLB")
86
87 sys = Param.System(Parent.any, "system object parameter")
88
89class ArmStage2IMMU(ArmStage2MMU):
90 # We rely on the itb being a parameter of the CPU, and get the
91 # appropriate object that way
92 tlb = Parent.itb
93 stage2_tlb = ArmStage2TLB()
94
95class ArmStage2DMMU(ArmStage2MMU):
96 # We rely on the dtb being a parameter of the CPU, and get the
97 # appropriate object that way
98 tlb = Parent.dtb
99 stage2_tlb = ArmStage2TLB()
|