3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software
9# licensed hereunder. You may use the software subject to the license
10# terms below provided that you ensure that this notice is replicated
11# unmodified and in its entirety in all distributions of the software,
12# modified or unmodified, in source code or in binary form.
13#
14# Redistribution and use in source and binary forms, with or without
15# modification, are permitted provided that the following conditions are
16# met: redistributions of source code must retain the above copyright
17# notice, this list of conditions and the following disclaimer;
18# redistributions in binary form must reproduce the above copyright
19# notice, this list of conditions and the following disclaimer in the
20# documentation and/or other materials provided with the distribution;
21# neither the name of the copyright holders nor the names of its
22# contributors may be used to endorse or promote products derived from
23# this software without specific prior written permission.
24#
25# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36#
37# Authors: Matt Horsnell
38# Andreas Sandberg
39
40from m5.defines import buildEnv
41from m5.SimObject import *
42from m5.params import *
43from m5.params import isNullPointer
44from m5.proxy import *
45
46class ArmPMU(SimObject):
47 type = 'ArmPMU'
48 cxx_class = 'ArmISA::PMU'
49 cxx_header = 'arch/arm/pmu.hh'
50
51 cxx_exports = [
52 PyBindMethod("addEventProbe"),
53 ]
54
55 # To prevent cycles in the configuration hierarchy, we don't keep
56 # a list of supported events as a configuration param. Instead, we
57 # keep them in a local list and register them using the
58 # addEventProbe interface when other SimObjects register their
59 # probe listeners.
60 _deferred_event_types = []
61 # Override the normal SimObject::regProbeListeners method and
62 # register deferred event handlers.
63 def regProbeListeners(self):
64 for event_id, obj, name in self._deferred_event_types:
65 self.getCCObject().addEventProbe(event_id, obj.getCCObject(), name)
66
67 self.getCCObject().regProbeListeners()
68
69 def addEventProbe(self, event_id, obj, *args):
70 """Add a probe-based event to the PMU if obj is not None."""
71
72 if obj is None:
73 return
74
75 for name in args:
76 self._deferred_event_types.append((event_id, obj, name))
77
78 def addArchEvents(self,
79 cpu=None,
80 itb=None, dtb=None,
81 icache=None, dcache=None,
82 l2cache=None):
83 """Add architected events to the PMU.
84
85 This method can be called multiple times with only a subset of
86 the keyword arguments set. This enables event registration in
87 configuration scripts to happen closer to the instantiation of
88 the instrumented objects (e.g., the memory system) instead of
89 a central point.
90
91 CPU events should also be registered once per CPU that is
92 sharing the PMU (e.g., when switching between CPU models).
93 """
94
95 bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
96 else None
97
98 # 0x01: L1I_CACHE_REFILL
99 self.addEventProbe(0x02, itb, "Refills")
| 3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software
9# licensed hereunder. You may use the software subject to the license
10# terms below provided that you ensure that this notice is replicated
11# unmodified and in its entirety in all distributions of the software,
12# modified or unmodified, in source code or in binary form.
13#
14# Redistribution and use in source and binary forms, with or without
15# modification, are permitted provided that the following conditions are
16# met: redistributions of source code must retain the above copyright
17# notice, this list of conditions and the following disclaimer;
18# redistributions in binary form must reproduce the above copyright
19# notice, this list of conditions and the following disclaimer in the
20# documentation and/or other materials provided with the distribution;
21# neither the name of the copyright holders nor the names of its
22# contributors may be used to endorse or promote products derived from
23# this software without specific prior written permission.
24#
25# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36#
37# Authors: Matt Horsnell
38# Andreas Sandberg
39
40from m5.defines import buildEnv
41from m5.SimObject import *
42from m5.params import *
43from m5.params import isNullPointer
44from m5.proxy import *
45
46class ArmPMU(SimObject):
47 type = 'ArmPMU'
48 cxx_class = 'ArmISA::PMU'
49 cxx_header = 'arch/arm/pmu.hh'
50
51 cxx_exports = [
52 PyBindMethod("addEventProbe"),
53 ]
54
55 # To prevent cycles in the configuration hierarchy, we don't keep
56 # a list of supported events as a configuration param. Instead, we
57 # keep them in a local list and register them using the
58 # addEventProbe interface when other SimObjects register their
59 # probe listeners.
60 _deferred_event_types = []
61 # Override the normal SimObject::regProbeListeners method and
62 # register deferred event handlers.
63 def regProbeListeners(self):
64 for event_id, obj, name in self._deferred_event_types:
65 self.getCCObject().addEventProbe(event_id, obj.getCCObject(), name)
66
67 self.getCCObject().regProbeListeners()
68
69 def addEventProbe(self, event_id, obj, *args):
70 """Add a probe-based event to the PMU if obj is not None."""
71
72 if obj is None:
73 return
74
75 for name in args:
76 self._deferred_event_types.append((event_id, obj, name))
77
78 def addArchEvents(self,
79 cpu=None,
80 itb=None, dtb=None,
81 icache=None, dcache=None,
82 l2cache=None):
83 """Add architected events to the PMU.
84
85 This method can be called multiple times with only a subset of
86 the keyword arguments set. This enables event registration in
87 configuration scripts to happen closer to the instantiation of
88 the instrumented objects (e.g., the memory system) instead of
89 a central point.
90
91 CPU events should also be registered once per CPU that is
92 sharing the PMU (e.g., when switching between CPU models).
93 """
94
95 bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
96 else None
97
98 # 0x01: L1I_CACHE_REFILL
99 self.addEventProbe(0x02, itb, "Refills")
|
101 # 0x04: L1D_CACHE
102 self.addEventProbe(0x05, dtb, "Refills")
103 self.addEventProbe(0x06, cpu, "RetiredLoads")
104 self.addEventProbe(0x07, cpu, "RetiredStores")
105 self.addEventProbe(0x08, cpu, "RetiredInsts")
106 # 0x09: EXC_TAKEN
107 # 0x0A: EXC_RETURN
108 # 0x0B: CID_WRITE_RETIRED
109 self.addEventProbe(0x0C, cpu, "RetiredBranches")
110 # 0x0D: BR_IMMED_RETIRED
111 # 0x0E: BR_RETURN_RETIRED
112 # 0x0F: UNALIGEND_LDST_RETIRED
113 self.addEventProbe(0x10, bpred, "Misses")
114 self.addEventProbe(0x11, cpu, "Cycles")
115 self.addEventProbe(0x12, bpred, "Branches")
116 self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
117 # 0x14: L1I_CACHE
118 # 0x15: L1D_CACHE_WB
119 # 0x16: L2D_CACHE
120 # 0x17: L2D_CACHE_REFILL
121 # 0x18: L2D_CACHE_WB
122 # 0x19: BUS_ACCESS
123 # 0x1A: MEMORY_ERROR
124 # 0x1B: INST_SPEC
125 # 0x1C: TTBR_WRITE_RETIRED
126 # 0x1D: BUS_CYCLES
127 # 0x1E: CHAIN
128 # 0x1F: L1D_CACHE_ALLOCATE
129 # 0x20: L2D_CACHE_ALLOCATE
| 101 # 0x04: L1D_CACHE
102 self.addEventProbe(0x05, dtb, "Refills")
103 self.addEventProbe(0x06, cpu, "RetiredLoads")
104 self.addEventProbe(0x07, cpu, "RetiredStores")
105 self.addEventProbe(0x08, cpu, "RetiredInsts")
106 # 0x09: EXC_TAKEN
107 # 0x0A: EXC_RETURN
108 # 0x0B: CID_WRITE_RETIRED
109 self.addEventProbe(0x0C, cpu, "RetiredBranches")
110 # 0x0D: BR_IMMED_RETIRED
111 # 0x0E: BR_RETURN_RETIRED
112 # 0x0F: UNALIGEND_LDST_RETIRED
113 self.addEventProbe(0x10, bpred, "Misses")
114 self.addEventProbe(0x11, cpu, "Cycles")
115 self.addEventProbe(0x12, bpred, "Branches")
116 self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
117 # 0x14: L1I_CACHE
118 # 0x15: L1D_CACHE_WB
119 # 0x16: L2D_CACHE
120 # 0x17: L2D_CACHE_REFILL
121 # 0x18: L2D_CACHE_WB
122 # 0x19: BUS_ACCESS
123 # 0x1A: MEMORY_ERROR
124 # 0x1B: INST_SPEC
125 # 0x1C: TTBR_WRITE_RETIRED
126 # 0x1D: BUS_CYCLES
127 # 0x1E: CHAIN
128 # 0x1F: L1D_CACHE_ALLOCATE
129 # 0x20: L2D_CACHE_ALLOCATE
|