1# -*- mode:python -*-
2# Copyright (c) 2009-2014, 2017 ARM Limited
3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software
9# licensed hereunder. You may use the software subject to the license
10# terms below provided that you ensure that this notice is replicated
11# unmodified and in its entirety in all distributions of the software,
12# modified or unmodified, in source code or in binary form.
13#
14# Redistribution and use in source and binary forms, with or without
15# modification, are permitted provided that the following conditions are
16# met: redistributions of source code must retain the above copyright
17# notice, this list of conditions and the following disclaimer;
18# redistributions in binary form must reproduce the above copyright
19# notice, this list of conditions and the following disclaimer in the
20# documentation and/or other materials provided with the distribution;
21# neither the name of the copyright holders nor the names of its
22# contributors may be used to endorse or promote products derived from
23# this software without specific prior written permission.
24#
25# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36#
37# Authors: Matt Horsnell
38# Andreas Sandberg
39
40from m5.defines import buildEnv
41from m5.SimObject import *
42from m5.params import *
43from m5.params import isNullPointer
44from m5.proxy import *
45
46class ProbeEvent(object):
47 def __init__(self, pmu, _eventId, obj, *listOfNames):
48 self.obj = obj
49 self.names = listOfNames
50 self.eventId = _eventId
51 self.pmu = pmu
52
53 def register(self):
54 if self.obj:
55 for name in self.names:
56 self.pmu.getCCObject().addEventProbe(self.eventId,
57 self.obj.getCCObject(), name)
58
59class SoftwareIncrement(object):
60 def __init__(self,pmu, _eventId):
61 self.eventId = _eventId
62 self.pmu = pmu
63
64 def register(self):
65 self.pmu.getCCObject().addSoftwareIncrementEvent(self.eventId)
66
67ARCH_EVENT_CORE_CYCLES = 0x11
68
69class ArmPMU(SimObject):
70
71 type = 'ArmPMU'
72 cxx_class = 'ArmISA::PMU'
73 cxx_header = 'arch/arm/pmu.hh'
74
75 cxx_exports = [
76 PyBindMethod("addEventProbe"),
77 PyBindMethod("addSoftwareIncrementEvent"),
78 ]
79
80 _events = None
81
82 def addEvent(self, newObject):
83 if not (isinstance(newObject, ProbeEvent)
84 or isinstance(newObject, SoftwareIncrement)):
85 raise TypeError("argument must be of ProbeEvent or "
86 "SoftwareIncrement type")
87
88 if not self._events:
89 self._events = []
90
91 self._events.append(newObject)
92
93 # Override the normal SimObject::regProbeListeners method and
94 # register deferred event handlers.
95 def regProbeListeners(self):
96 for event in self._events:
97 event.register()
98
99 self.getCCObject().regProbeListeners()
100
101 def addArchEvents(self,
102 cpu=None,
103 itb=None, dtb=None,
104 icache=None, dcache=None,
105 l2cache=None):
106 """Add architected events to the PMU.
107
108 This method can be called multiple times with only a subset of
109 the keyword arguments set. This enables event registration in
110 configuration scripts to happen closer to the instantiation of
111 the instrumented objects (e.g., the memory system) instead of
112 a central point.
113
114 CPU events should also be registered once per CPU that is
115 sharing the PMU (e.g., when switching between CPU models).
116 """
117
118 bpred = getattr(cpu, "branchPred", None) if cpu else None
119 if bpred is not None and isNullPointer(bpred):
120 bpred = None
121
122 self.addEvent(SoftwareIncrement(self,0x00))
123 # 0x01: L1I_CACHE_REFILL
124 self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
125 # 0x03: L1D_CACHE_REFILL
126 # 0x04: L1D_CACHE
127 self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
128 self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
129 self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
130 self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
131 # 0x09: EXC_TAKEN
132 # 0x0A: EXC_RETURN
133 # 0x0B: CID_WRITE_RETIRED
134 self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches"))
135 # 0x0D: BR_IMMED_RETIRED
136 # 0x0E: BR_RETURN_RETIRED
137 # 0x0F: UNALIGEND_LDST_RETIRED
138 self.addEvent(ProbeEvent(self,0x10, bpred, "Misses"))
139 self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
140 "ActiveCycles"))
141 self.addEvent(ProbeEvent(self,0x12, bpred, "Branches"))
142 self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",
143 "RetiredStores"))
144 # 0x14: L1I_CACHE
145 # 0x15: L1D_CACHE_WB
146 # 0x16: L2D_CACHE
147 # 0x17: L2D_CACHE_REFILL
148 # 0x18: L2D_CACHE_WB
149 # 0x19: BUS_ACCESS
150 # 0x1A: MEMORY_ERROR
151 # 0x1B: INST_SPEC
152 # 0x1C: TTBR_WRITE_RETIRED
153 # 0x1D: BUS_CYCLES
154 # 0x1E: CHAIN
155 # 0x1F: L1D_CACHE_ALLOCATE
156 # 0x20: L2D_CACHE_ALLOCATE
157 # 0x21: BR_RETIRED
158 # 0x22: BR_MIS_PRED_RETIRED
159 # 0x23: STALL_FRONTEND
160 # 0x24: STALL_BACKEND
161 # 0x25: L1D_TLB
162 # 0x26: L1I_TLB
163 # 0x27: L2I_CACHE
164 # 0x28: L2I_CACHE_REFILL
165 # 0x29: L3D_CACHE_ALLOCATE
166 # 0x2A: L3D_CACHE_REFILL
167 # 0x2B: L3D_CACHE
168 # 0x2C: L3D_CACHE_WB
169 # 0x2D: L2D_TLB_REFILL
170 # 0x2E: L2I_TLB_REFILL
171 # 0x2F: L2D_TLB
172 # 0x30: L2I_TLB
173
174 cycleEventId = Param.Int(ARCH_EVENT_CORE_CYCLES, "Cycle event id")
175 platform = Param.Platform(Parent.any, "Platform this device is part of.")
176 eventCounters = Param.Int(31, "Number of supported PMU counters")
177 pmuInterrupt = Param.Int(68, "PMU GIC interrupt number")
2# Copyright (c) 2009-2014, 2017 ARM Limited
3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software
9# licensed hereunder. You may use the software subject to the license
10# terms below provided that you ensure that this notice is replicated
11# unmodified and in its entirety in all distributions of the software,
12# modified or unmodified, in source code or in binary form.
13#
14# Redistribution and use in source and binary forms, with or without
15# modification, are permitted provided that the following conditions are
16# met: redistributions of source code must retain the above copyright
17# notice, this list of conditions and the following disclaimer;
18# redistributions in binary form must reproduce the above copyright
19# notice, this list of conditions and the following disclaimer in the
20# documentation and/or other materials provided with the distribution;
21# neither the name of the copyright holders nor the names of its
22# contributors may be used to endorse or promote products derived from
23# this software without specific prior written permission.
24#
25# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36#
37# Authors: Matt Horsnell
38# Andreas Sandberg
39
40from m5.defines import buildEnv
41from m5.SimObject import *
42from m5.params import *
43from m5.params import isNullPointer
44from m5.proxy import *
45
46class ProbeEvent(object):
47 def __init__(self, pmu, _eventId, obj, *listOfNames):
48 self.obj = obj
49 self.names = listOfNames
50 self.eventId = _eventId
51 self.pmu = pmu
52
53 def register(self):
54 if self.obj:
55 for name in self.names:
56 self.pmu.getCCObject().addEventProbe(self.eventId,
57 self.obj.getCCObject(), name)
58
59class SoftwareIncrement(object):
60 def __init__(self,pmu, _eventId):
61 self.eventId = _eventId
62 self.pmu = pmu
63
64 def register(self):
65 self.pmu.getCCObject().addSoftwareIncrementEvent(self.eventId)
66
67ARCH_EVENT_CORE_CYCLES = 0x11
68
69class ArmPMU(SimObject):
70
71 type = 'ArmPMU'
72 cxx_class = 'ArmISA::PMU'
73 cxx_header = 'arch/arm/pmu.hh'
74
75 cxx_exports = [
76 PyBindMethod("addEventProbe"),
77 PyBindMethod("addSoftwareIncrementEvent"),
78 ]
79
80 _events = None
81
82 def addEvent(self, newObject):
83 if not (isinstance(newObject, ProbeEvent)
84 or isinstance(newObject, SoftwareIncrement)):
85 raise TypeError("argument must be of ProbeEvent or "
86 "SoftwareIncrement type")
87
88 if not self._events:
89 self._events = []
90
91 self._events.append(newObject)
92
93 # Override the normal SimObject::regProbeListeners method and
94 # register deferred event handlers.
95 def regProbeListeners(self):
96 for event in self._events:
97 event.register()
98
99 self.getCCObject().regProbeListeners()
100
101 def addArchEvents(self,
102 cpu=None,
103 itb=None, dtb=None,
104 icache=None, dcache=None,
105 l2cache=None):
106 """Add architected events to the PMU.
107
108 This method can be called multiple times with only a subset of
109 the keyword arguments set. This enables event registration in
110 configuration scripts to happen closer to the instantiation of
111 the instrumented objects (e.g., the memory system) instead of
112 a central point.
113
114 CPU events should also be registered once per CPU that is
115 sharing the PMU (e.g., when switching between CPU models).
116 """
117
118 bpred = getattr(cpu, "branchPred", None) if cpu else None
119 if bpred is not None and isNullPointer(bpred):
120 bpred = None
121
122 self.addEvent(SoftwareIncrement(self,0x00))
123 # 0x01: L1I_CACHE_REFILL
124 self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
125 # 0x03: L1D_CACHE_REFILL
126 # 0x04: L1D_CACHE
127 self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
128 self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
129 self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
130 self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
131 # 0x09: EXC_TAKEN
132 # 0x0A: EXC_RETURN
133 # 0x0B: CID_WRITE_RETIRED
134 self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches"))
135 # 0x0D: BR_IMMED_RETIRED
136 # 0x0E: BR_RETURN_RETIRED
137 # 0x0F: UNALIGEND_LDST_RETIRED
138 self.addEvent(ProbeEvent(self,0x10, bpred, "Misses"))
139 self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
140 "ActiveCycles"))
141 self.addEvent(ProbeEvent(self,0x12, bpred, "Branches"))
142 self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",
143 "RetiredStores"))
144 # 0x14: L1I_CACHE
145 # 0x15: L1D_CACHE_WB
146 # 0x16: L2D_CACHE
147 # 0x17: L2D_CACHE_REFILL
148 # 0x18: L2D_CACHE_WB
149 # 0x19: BUS_ACCESS
150 # 0x1A: MEMORY_ERROR
151 # 0x1B: INST_SPEC
152 # 0x1C: TTBR_WRITE_RETIRED
153 # 0x1D: BUS_CYCLES
154 # 0x1E: CHAIN
155 # 0x1F: L1D_CACHE_ALLOCATE
156 # 0x20: L2D_CACHE_ALLOCATE
157 # 0x21: BR_RETIRED
158 # 0x22: BR_MIS_PRED_RETIRED
159 # 0x23: STALL_FRONTEND
160 # 0x24: STALL_BACKEND
161 # 0x25: L1D_TLB
162 # 0x26: L1I_TLB
163 # 0x27: L2I_CACHE
164 # 0x28: L2I_CACHE_REFILL
165 # 0x29: L3D_CACHE_ALLOCATE
166 # 0x2A: L3D_CACHE_REFILL
167 # 0x2B: L3D_CACHE
168 # 0x2C: L3D_CACHE_WB
169 # 0x2D: L2D_TLB_REFILL
170 # 0x2E: L2I_TLB_REFILL
171 # 0x2F: L2D_TLB
172 # 0x30: L2I_TLB
173
174 cycleEventId = Param.Int(ARCH_EVENT_CORE_CYCLES, "Cycle event id")
175 platform = Param.Platform(Parent.any, "Platform this device is part of.")
176 eventCounters = Param.Int(31, "Number of supported PMU counters")
177 pmuInterrupt = Param.Int(68, "PMU GIC interrupt number")