1# -*- mode:python -*-
2# Copyright (c) 2009-2014, 2017 ARM Limited
3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software

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38# Andreas Sandberg
39
40from m5.defines import buildEnv
41from m5.SimObject import *
42from m5.params import *
43from m5.params import isNullPointer
44from m5.proxy import *
45
46class ArmPMU(SimObject):
47 type = 'ArmPMU'
48 cxx_class = 'ArmISA::PMU'
49 cxx_header = 'arch/arm/pmu.hh'
50
51 cxx_exports = [
52 PyBindMethod("addEventProbe"),
53 ]
54
55 # To prevent cycles in the configuration hierarchy, we don't keep
56 # a list of supported events as a configuration param. Instead, we
57 # keep them in a local list and register them using the
58 # addEventProbe interface when other SimObjects register their
59 # probe listeners.
60 _deferred_event_types = []
61 # Override the normal SimObject::regProbeListeners method and
62 # register deferred event handlers.
63 def regProbeListeners(self):
64 for event_id, obj, name in self._deferred_event_types:
65 self.getCCObject().addEventProbe(event_id, obj.getCCObject(), name)
66
67 self.getCCObject().regProbeListeners()
68
69 def addEventProbe(self, event_id, obj, *args):
70 """Add a probe-based event to the PMU if obj is not None."""
71
72 if obj is None:
73 return
74
75 for name in args:
76 self._deferred_event_types.append((event_id, obj, name))
77
78 def addArchEvents(self,
79 cpu=None,
80 itb=None, dtb=None,
81 icache=None, dcache=None,
82 l2cache=None):
83 """Add architected events to the PMU.
84
85 This method can be called multiple times with only a subset of

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90
91 CPU events should also be registered once per CPU that is
92 sharing the PMU (e.g., when switching between CPU models).
93 """
94
95 bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
96 else None
97
98 # 0x01: L1I_CACHE_REFILL
99 self.addEventProbe(0x02, itb, "Refills")
100 # 0x03: L1D_CACHE_REFILL
101 # 0x04: L1D_CACHE
102 self.addEventProbe(0x05, dtb, "Refills")
103 self.addEventProbe(0x06, cpu, "RetiredLoads")
104 self.addEventProbe(0x07, cpu, "RetiredStores")
105 self.addEventProbe(0x08, cpu, "RetiredInsts")
106 # 0x09: EXC_TAKEN
107 # 0x0A: EXC_RETURN
108 # 0x0B: CID_WRITE_RETIRED
109 self.addEventProbe(0x0C, cpu, "RetiredBranches")
110 # 0x0D: BR_IMMED_RETIRED
111 # 0x0E: BR_RETURN_RETIRED
112 # 0x0F: UNALIGEND_LDST_RETIRED
113 self.addEventProbe(0x10, bpred, "Misses")
114 self.addEventProbe(0x11, cpu, "ActiveCycles")
115 self.addEventProbe(0x12, bpred, "Branches")
116 self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
117 # 0x14: L1I_CACHE
118 # 0x15: L1D_CACHE_WB
119 # 0x16: L2D_CACHE
120 # 0x17: L2D_CACHE_REFILL
121 # 0x18: L2D_CACHE_WB
122 # 0x19: BUS_ACCESS
123 # 0x1A: MEMORY_ERROR
124 # 0x1B: INST_SPEC

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139 # 0x2A: L3D_CACHE_REFILL
140 # 0x2B: L3D_CACHE
141 # 0x2C: L3D_CACHE_WB
142 # 0x2D: L2D_TLB_REFILL
143 # 0x2E: L2I_TLB_REFILL
144 # 0x2F: L2D_TLB
145 # 0x30: L2I_TLB
146
147 platform = Param.Platform(Parent.any, "Platform this device is part of.")
148 eventCounters = Param.Int(31, "Number of supported PMU counters")
149 pmuInterrupt = Param.Int(68, "PMU GIC interrupt number")