ArmISA.py (9385:25ebe5e13a07) ArmISA.py (10037:5cac77888310)
1# Copyright (c) 2012 ARM Limited
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 19 unchanged lines hidden (view full) ---

29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Giacomo Gabrielli
37
38from m5.params import *
38
39from m5.params import *
40from m5.proxy import *
39from m5.SimObject import SimObject
40
41class ArmISA(SimObject):
42 type = 'ArmISA'
43 cxx_class = 'ArmISA::ISA'
44 cxx_header = "arch/arm/isa.hh"
45
41from m5.SimObject import SimObject
42
43class ArmISA(SimObject):
44 type = 'ArmISA'
45 cxx_class = 'ArmISA::ISA'
46 cxx_header = "arch/arm/isa.hh"
47
46 # 0x35 Implementor is '5' from "M5"
47 # 0x0 Variant
48 # 0xf Architecture from CPUID scheme
49 # 0xc00 Primary part number ("c" or higher implies ARM v7)
50 # 0x0 Revision
51 midr = Param.UInt32(0x350fc000, "Main ID Register")
48 system = Param.System(Parent.any, "System this ISA object belongs to")
52
49
50 midr = Param.UInt32(0x410fc0f0, "MIDR value")
51
53 # See section B4.1.93 - B4.1.94 of the ARM ARM
54 #
55 # !ThumbEE | !Jazelle | Thumb | ARM
56 # Note: ThumbEE is disabled for now since we don't support CP14
57 # config registers and jumping to ThumbEE vectors
58 id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
52 # See section B4.1.93 - B4.1.94 of the ARM ARM
53 #
54 # !ThumbEE | !Jazelle | Thumb | ARM
55 # Note: ThumbEE is disabled for now since we don't support CP14
56 # config registers and jumping to ThumbEE vectors
57 id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
59 # !Timer | !Virti | !M Profile | !TrustZone | ARMv4
60 id_pfr1 = Param.UInt32(0x00000001, "Processor Feature Register 1")
58 # !Timer | Virti | !M Profile | TrustZone | ARMv4
59 id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1")
61
62 # See section B4.1.89 - B4.1.92 of the ARM ARM
63 # VMSAv7 support
60
61 # See section B4.1.89 - B4.1.92 of the ARM ARM
62 # VMSAv7 support
64 id_mmfr0 = Param.UInt32(0x00000003, "Memory Model Feature Register 0")
63 id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
65 id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
66 # no HW access | WFI stalling | ISB and DSB |
67 # all TLB maintenance | no Harvard
68 id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
69 # SuperSec | Coherent TLB | Bcast Maint |
70 # BP Maint | Cache Maint Set/way | Cache Maint MVA
64 id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
65 # no HW access | WFI stalling | ISB and DSB |
66 # all TLB maintenance | no Harvard
67 id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
68 # SuperSec | Coherent TLB | Bcast Maint |
69 # BP Maint | Cache Maint Set/way | Cache Maint MVA
71 id_mmfr3 = Param.UInt32(0xF0102211, "Memory Model Feature Register 3")
70 id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
72
73 # See section B4.1.84 of ARM ARM
74 # All values are latest for ARMv7-A profile
75 id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
76 id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
77 id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
78 id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
79 id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
80 id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
81
71
72 # See section B4.1.84 of ARM ARM
73 # All values are latest for ARMv7-A profile
74 id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
75 id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
76 id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
77 id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
78 id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
79 id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
80
81 fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
82
82
83 fpsid = Param.UInt32(0x410430A0, "Floating-point System ID Register")
83 # [31:0] is implementation defined
84 id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
85 "AArch64 Auxiliary Feature Register 0")
86 # Reserved for future expansion
87 id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
88 "AArch64 Auxiliary Feature Register 1")
89
90 # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
91 id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
92 "AArch64 Debug Feature Register 0")
93 # Reserved for future expansion
94 id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
95 "AArch64 Debug Feature Register 1")
96
97 # !CRC32 | !SHA2 | !SHA1 | !AES
98 id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
99 "AArch64 Instruction Set Attribute Register 0")
100 # Reserved for future expansion
101 id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
102 "AArch64 Instruction Set Attribute Register 1")
103
104 # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
105 id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
106 "AArch64 Memory Model Feature Register 0")
107 # Reserved for future expansion
108 id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
109 "AArch64 Memory Model Feature Register 1")
110
111 # !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
112 # (no AArch32/64 interprocessing support for now)
113 id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011,
114 "AArch64 Processor Feature Register 0")
115 # Reserved for future expansion
116 id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
117 "AArch64 Processor Feature Register 1")