Cross Reference: /gem5/src/arch/arm/ArmISA.py

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ArmISA.py (14095:4f5d16d7cf45)	ArmISA.py (14128:6ed23d07d0d1)
1# Copyright (c) 2012-2013, 2015-2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 91 unchanged lines hidden (view full) --- 100 "AArch64 Instruction Set Attribute Register 0") 101 # Reserved for future expansion 102 id_aa64isar1_el1 = Param.UInt64(0x0000000000000000, 103 "AArch64 Instruction Set Attribute Register 1") 104 105 # 4K \| 64K \| !16K \| !BigEndEL0 \| !SNSMem \| !BigEnd \| 8b ASID \| 40b PA 106 id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002, 107 "AArch64 Memory Model Feature Register 0")	1# Copyright (c) 2012-2013, 2015-2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 91 unchanged lines hidden (view full) --- 100 "AArch64 Instruction Set Attribute Register 0") 101 # Reserved for future expansion 102 id_aa64isar1_el1 = Param.UInt64(0x0000000000000000, 103 "AArch64 Instruction Set Attribute Register 1") 104 105 # 4K \| 64K \| !16K \| !BigEndEL0 \| !SNSMem \| !BigEnd \| 8b ASID \| 40b PA 106 id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002, 107 "AArch64 Memory Model Feature Register 0")
108 # HPDS 109 id_aa64mmfr1_el1 = Param.UInt64(0x0000000000001000,	108 # PAN \| HPDS 109 id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
110 "AArch64 Memory Model Feature Register 1") 111 id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000, 112 "AArch64 Memory Model Feature Register 2") 113 114 # Any access (read/write) to an unimplemented 115 # Implementation Defined registers is not causing an Undefined Instruction. 116 # It is rather executed as a NOP. 117 impdef_nop = Param.Bool(False, 118 "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP") 119 120 # This is required because in SE mode a generic System SimObject is 121 # allocated, instead of an ArmSystem 122 sve_vl_se = Param.SveVectorLength(1, 123 "SVE vector length in quadwords (128-bit), SE-mode only")	110 "AArch64 Memory Model Feature Register 1") 111 id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000, 112 "AArch64 Memory Model Feature Register 2") 113 114 # Any access (read/write) to an unimplemented 115 # Implementation Defined registers is not causing an Undefined Instruction. 116 # It is rather executed as a NOP. 117 impdef_nop = Param.Bool(False, 118 "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP") 119 120 # This is required because in SE mode a generic System SimObject is 121 # allocated, instead of an ArmSystem 122 sve_vl_se = Param.SveVectorLength(1, 123 "SVE vector length in quadwords (128-bit), SE-mode only")