Cross Reference: /gem5/src/arch/arm/ArmISA.py

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ArmISA.py (10037:5cac77888310)	ArmISA.py (10461:afeb5cdb3907)
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37# Giacomo Gabrielli 38 39from m5.params import * 40from m5.proxy import * 41from m5.SimObject import SimObject 42	1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37# Giacomo Gabrielli 38 39from m5.params import * 40from m5.proxy import * 41from m5.SimObject import SimObject 42
	43from ArmPMU import ArmPMU 44
43class ArmISA(SimObject): 44 type = 'ArmISA' 45 cxx_class = 'ArmISA::ISA' 46 cxx_header = "arch/arm/isa.hh" 47 48 system = Param.System(Parent.any, "System this ISA object belongs to") 49	45class ArmISA(SimObject): 46 type = 'ArmISA' 47 cxx_class = 'ArmISA::ISA' 48 cxx_header = "arch/arm/isa.hh" 49 50 system = Param.System(Parent.any, "System this ISA object belongs to") 51
	52 pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit") 53
50 midr = Param.UInt32(0x410fc0f0, "MIDR value") 51 52 # See section B4.1.93 - B4.1.94 of the ARM ARM 53 # 54 # !ThumbEE \| !Jazelle \| Thumb \| ARM 55 # Note: ThumbEE is disabled for now since we don't support CP14 56 # config registers and jumping to ThumbEE vectors 57 id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0") 58 # !Timer \| Virti \| !M Profile \| TrustZone \| ARMv4 59 id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1") 60 61 # See section B4.1.89 - B4.1.92 of the ARM ARM 62 # VMSAv7 support 63 id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0") 64 id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1") 65 # no HW access \| WFI stalling \| ISB and DSB \| 66 # all TLB maintenance \| no Harvard 67 id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2") 68 # SuperSec \| Coherent TLB \| Bcast Maint \| 69 # BP Maint \| Cache Maint Set/way \| Cache Maint MVA 70 id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3") 71 72 # See section B4.1.84 of ARM ARM 73 # All values are latest for ARMv7-A profile 74 id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0") 75 id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1") 76 id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2") 77 id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3") 78 id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4") 79 id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5") 80 81 fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register") 82 83 # [31:0] is implementation defined 84 id_aa64afr0_el1 = Param.UInt64(0x0000000000000000, 85 "AArch64 Auxiliary Feature Register 0") 86 # Reserved for future expansion 87 id_aa64afr1_el1 = Param.UInt64(0x0000000000000000, 88 "AArch64 Auxiliary Feature Register 1") 89 90 # 1 CTX CMPs \| 2 WRPs \| 2 BRPs \| !PMU \| !Trace \| Debug v8-A 91 id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006, 92 "AArch64 Debug Feature Register 0") 93 # Reserved for future expansion 94 id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000, 95 "AArch64 Debug Feature Register 1") 96 97 # !CRC32 \| !SHA2 \| !SHA1 \| !AES 98 id_aa64isar0_el1 = Param.UInt64(0x0000000000000000, 99 "AArch64 Instruction Set Attribute Register 0") 100 # Reserved for future expansion 101 id_aa64isar1_el1 = Param.UInt64(0x0000000000000000, 102 "AArch64 Instruction Set Attribute Register 1") 103 104 # 4K \| 64K \| !16K \| !BigEndEL0 \| !SNSMem \| !BigEnd \| 8b ASID \| 40b PA 105 id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002, 106 "AArch64 Memory Model Feature Register 0") 107 # Reserved for future expansion 108 id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000, 109 "AArch64 Memory Model Feature Register 1") 110 111 # !GICv3 CP15 \| AdvSIMD \| FP \| !EL3 \| !EL2 \| EL1 (AArch64) \| EL0 (AArch64) 112 # (no AArch32/64 interprocessing support for now) 113 id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011, 114 "AArch64 Processor Feature Register 0") 115 # Reserved for future expansion 116 id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000, 117 "AArch64 Processor Feature Register 1")	54 midr = Param.UInt32(0x410fc0f0, "MIDR value") 55 56 # See section B4.1.93 - B4.1.94 of the ARM ARM 57 # 58 # !ThumbEE \| !Jazelle \| Thumb \| ARM 59 # Note: ThumbEE is disabled for now since we don't support CP14 60 # config registers and jumping to ThumbEE vectors 61 id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0") 62 # !Timer \| Virti \| !M Profile \| TrustZone \| ARMv4 63 id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1") 64 65 # See section B4.1.89 - B4.1.92 of the ARM ARM 66 # VMSAv7 support 67 id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0") 68 id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1") 69 # no HW access \| WFI stalling \| ISB and DSB \| 70 # all TLB maintenance \| no Harvard 71 id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2") 72 # SuperSec \| Coherent TLB \| Bcast Maint \| 73 # BP Maint \| Cache Maint Set/way \| Cache Maint MVA 74 id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3") 75 76 # See section B4.1.84 of ARM ARM 77 # All values are latest for ARMv7-A profile 78 id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0") 79 id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1") 80 id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2") 81 id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3") 82 id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4") 83 id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5") 84 85 fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register") 86 87 # [31:0] is implementation defined 88 id_aa64afr0_el1 = Param.UInt64(0x0000000000000000, 89 "AArch64 Auxiliary Feature Register 0") 90 # Reserved for future expansion 91 id_aa64afr1_el1 = Param.UInt64(0x0000000000000000, 92 "AArch64 Auxiliary Feature Register 1") 93 94 # 1 CTX CMPs \| 2 WRPs \| 2 BRPs \| !PMU \| !Trace \| Debug v8-A 95 id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006, 96 "AArch64 Debug Feature Register 0") 97 # Reserved for future expansion 98 id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000, 99 "AArch64 Debug Feature Register 1") 100 101 # !CRC32 \| !SHA2 \| !SHA1 \| !AES 102 id_aa64isar0_el1 = Param.UInt64(0x0000000000000000, 103 "AArch64 Instruction Set Attribute Register 0") 104 # Reserved for future expansion 105 id_aa64isar1_el1 = Param.UInt64(0x0000000000000000, 106 "AArch64 Instruction Set Attribute Register 1") 107 108 # 4K \| 64K \| !16K \| !BigEndEL0 \| !SNSMem \| !BigEnd \| 8b ASID \| 40b PA 109 id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002, 110 "AArch64 Memory Model Feature Register 0") 111 # Reserved for future expansion 112 id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000, 113 "AArch64 Memory Model Feature Register 1") 114 115 # !GICv3 CP15 \| AdvSIMD \| FP \| !EL3 \| !EL2 \| EL1 (AArch64) \| EL0 (AArch64) 116 # (no AArch32/64 interprocessing support for now) 117 id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011, 118 "AArch64 Processor Feature Register 0") 119 # Reserved for future expansion 120 id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000, 121 "AArch64 Processor Feature Register 1")