utility.hh (6330:786136379872) utility.hh (7627:3b0c4b819651)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46inline bool
47inUserMode(ThreadContext *tc)
48{
49 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
50}
51
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46inline bool
47inUserMode(ThreadContext *tc)
48{
49 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
50}
51
52inline bool
53isCallerSaveIntegerRegister(unsigned int reg)
54{
55 panic("register classification not implemented");
56 return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
57}
58
59inline bool
60isCalleeSaveIntegerRegister(unsigned int reg)
61{
62 panic("register classification not implemented");
63 return reg >= 9 && reg <= 15;
64}
65
66inline bool
67isCallerSaveFloatRegister(unsigned int reg)
68{
69 panic("register classification not implemented");
70 return false;
71}
72
73inline bool
74isCalleeSaveFloatRegister(unsigned int reg)
75{
76 panic("register classification not implemented");
77 return false;
78}
79
80inline Addr
81alignAddress(const Addr &addr, unsigned int nbytes)
82{
83 return (addr & ~(nbytes - 1));
84}
85
86// Instruction address compression hooks
87inline Addr
88realPCToFetchPC(const Addr &addr)
89{
90 return addr;
91}
92
93inline Addr
94fetchPCToRealPC(const Addr &addr)
95{
96 return addr;
97}
98
99// the size of "fetched" instructions (not necessarily the size
100// of real instructions for PISA)
101inline size_t
102fetchInstSize()
103{
104 return sizeof(MachInst);
105}
106
107inline MachInst
108makeRegisterCopy(int dest, int src)
109{
110 panic("makeRegisterCopy not implemented");
111 return 0;
112}
113
114/**
115 * Function to insure ISA semantics about 0 registers.
116 * @param tc The thread context.
117 */
118template <class TC>
119void zeroRegisters(TC *tc);
120
121// Alpha IPR register accessors

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145
146inline Addr
147RoundPage(Addr addr)
148{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
149
150void initIPRs(ThreadContext *tc, int cpuId);
151#if FULL_SYSTEM
152void initCPU(ThreadContext *tc, int cpuId);
52/**
53 * Function to insure ISA semantics about 0 registers.
54 * @param tc The thread context.
55 */
56template <class TC>
57void zeroRegisters(TC *tc);
58
59// Alpha IPR register accessors

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83
84inline Addr
85RoundPage(Addr addr)
86{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
87
88void initIPRs(ThreadContext *tc, int cpuId);
89#if FULL_SYSTEM
90void initCPU(ThreadContext *tc, int cpuId);
153
154/**
155 * Function to check for and process any interrupts.
156 * @param tc The thread context.
157 */
158template <class TC>
159void processInterrupts(TC *tc);
160#endif
161
162void copyRegs(ThreadContext *src, ThreadContext *dest);
163
164void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
165
166} // namespace AlphaISA
167
168#endif // __ARCH_ALPHA_UTILITY_HH__
91#endif
92
93void copyRegs(ThreadContext *src, ThreadContext *dest);
94
95void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
96
97} // namespace AlphaISA
98
99#endif // __ARCH_ALPHA_UTILITY_HH__